View 56F8035_4673454.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

56F8035/56F8025
Data Sheet Technical Data
56F8000 16-bit Digital Signal Controllers
MC56F8025 Rev. 6 02/2010
freescale.com
Document Revision History
Version History Rev. 0 Rev. 1 Initial public release. * In Table 5-3, changed the ITCN_BASE address from $00 F060 (incorrect value) to $00 F0E0 (the correct value). * In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). * In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. * In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. * Changed input propagation delay values in Table 10-20 as follows: Old values: 1 s typical, 2 s maximum New values: 35 ns typical, 45 ns maximum Rev. 2 * In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. * Replaced the case outline schematics in Figure 11-2, Figure 11-3, and Figure 11-4. Rev. 3 Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. * Changed the VBA register reset value and updated the footnote in Section 5.6.8. * Changed the STANDBY > STOP IDD values in Table 10-6 as follows: Typical: was 290A, is 540A Maximum: was 390A, is 650A * Changed the POWERDOWN IDD values in Table 10-6 as follows: Typical: was 190A, is 440A Maximum: was 250A, is 550A * Changed footnote 1 in Table 10-12 (was "Output frequency after application of 8MHz trim value, at 125C.", is "Output frequency after application of factory trim"). * Deleted the text "at 125C" from Figure 10-5. * Changed the maximum input offset voltage in Table 10-20 (was +/- 20 mV, is 35 mV). Rev. 5 * In Table 2-3, change VCAP value from 4.7F to 2.2F. * Revised Section 7, Security Features. * Fixed miscellaneous typos. Description of Change
Rev. 4
56F8035/56F8025 Data Sheet, Rev. 6 2 Freescale Semiconductor
Document Revision History
Version History Rev. 6 Description of Change In the table Recommended Operating Conditions, removed the line "XTAL not driven by an external clock" from the characteristic: "Oscillator Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source" Changed COUTB_A to CMPBO throughout Added MC56F8035 device Added MC56F8025MLD to the orderable parts In the System Integration Module (SIM) chapter, fixed typos Added IPS0_PSRC2 field to SIM_IPS0 register
Please see http://www.freescale.com for the most current data sheet revision.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 3
56F8035/56F8025 General Description
* Up to 32 MIPS at 32MHz core frequency * DSP and MCU functionality in a unified, C-efficient architecture * 56F8035 offers 64KB (32K x 16) Program Flash * 56F8025 offers 32KB (16K x 16) Program Flash * 56F8035 offers 8KB (4K x 16) Unified Data/Program RAM * 56F8025 offers 4KB (2K x 16) Unified Data/Program RAM * One 6-channel PWM module * Two 4-channel 12-bit Analog-to-Digital Converters (ADCs) * Two Internal 12-bit Digital-to-Analog Converters (DACs) * Two Analog Comparators * Three Programmable Interval Timers (PITs) * One Queued Serial Communication Interface (QSCI) with LIN slave functionality * One Queued Serial Peripheral Interfaces (QSPI) * One 16-bit Quad Timer * One Inter-Integrated Circuit (I2C) port * Computer Operating Properly (COP)/Watchdog * On-Chip Relaxation Oscillator * Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module * JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging * Up to 35 GPIO lines
RESET or GPIOA 4
VCAP 2
VDD 2
VSS 3
VDDA
VSSA
11
PWM or TMRA or CMP or GPIOA
Program Controller and Hardware Looping Unit
JTAG/EOnCE Port or GPIOD
Digital Reg
Analog Reg
16-Bit 56800E Core
Low-Voltage Supervisor Bit Manipulation Unit
Address Generation Unit
Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
DAC 4
PAB PDB CDBR CDBW
AD0 ADC or CMP or GPIOC
Memory
Program Memory 16K x 16 Flash 32K x 16 Flash Unified Data / Program RAM 2K x 16 4K x 16
XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
R/W Control
4
AD1
System Bus Control
Programmable Interval Timer
IPBus Bridge (IPBB)
I2C or CMP or GPIOB
QSPI or PWM or I2C or TMRA or GPIOB 4
QSCI or PWM or I2C or TMRA or GPIOB
COP/ Watchdog
Interrupt Controller
System Integration Module
P O R
O Clock S Generator* C
XTAL, CLKIN, or GPIOD EXTAL or GPIOD
2
3
*Includes On-Chip Relaxation Oscillator
56F8035/56F8025 Block Diagram
56F8035/56F8025 Data Sheet, Rev. 6 4 Freescale Semiconductor
56F8035/56F8025 Data Sheet Table of Contents
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 1.3 1.4 1.5 1.6 56F8035/56F8025 Features . . . . . . . . . . . 6 56F8035/56F8025 Description . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 9 Architecture Block Diagram . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . 17 Data Sheet Conventions . . . . . . . . . . . . . 17 7.3 Product Analysis. . . . . . . . . . . . . . . . . . 114
Part 8 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . .114
8.1 8.2 8.3 Introduction. . . . . . . . . . . . . . . . . . . . . . 114 Configuration . . . . . . . . . . . . . . . . . . . . 114 Reset Values . . . . . . . . . . . . . . . . . . . . 117
Part 9 Joint Test Action Group (JTAG) . . .122 Part 2 Signal/Connection Descriptions . . . 18
2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . 18 56F8035/56F8025 Signal Pins . . . . . . . . 22 9.1 56F8035/56F8025 Information . . . . . . . 122
Part 10Specifications. . . . . . . . . . . . . . . . . .122
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 General Characteristics . . . . . . . . . . . . 122 DC Electrical Characteristics . . . . . . . . 126 AC Electrical Characteristics . . . . . . . . 129 Flash Memory Characteristics . . . . . . . 130 External Clock Operation Timing . . . . . 130 Phase Locked Loop Timing . . . . . . . . . 131 Relaxation Oscillator Timing. . . . . . . . . 132 Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 133 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . . . . . 134 Quad Timer Timing. . . . . . . . . . . . . . . . 138 Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . 140 Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . . . . . . . . . . . . . . . 141 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 143 Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . . 144 Equivalent Circuit for ADC Inputs . . . . . 145 Comparator (CMP) Parameters . . . . . . 146 Digital-to-Analog Converter (DAC) Parameters . . . . . . . . . . . . . . . . . 146 Power Consumption . . . . . . . . . . . . . . . 148
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 33 Features . . . . . . . . . . . . . . . . . . . . . . . . . 33 Operating Modes . . . . . . . . . . . . . . . . . . 33 Internal Clock Source . . . . . . . . . . . . . . . 34 Crystal Oscillator. . . . . . . . . . . . . . . . . . . 34 Ceramic Resonator . . . . . . . . . . . . . . . . . 35 External Clock Input - Crystal Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . 35 Alternate External Clock Input . . . . . . . . 36
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 36
4.1 4.2 4.3 4.4 4.5 4.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Vector Table . . . . . . . . . . . . . . . 37 Program Map . . . . . . . . . . . . . . . . . . . . . 39 Data Map . . . . . . . . . . . . . . . . . . . . . . . . 39 EOnCE Memory Map . . . . . . . . . . . . . . . 41 Peripheral Memory-Mapped Registers . . 42
Part 5 Interrupt Controller (ITCN) . . . . . . . . 56
5.1 5.2 5.3 5.4 5.5 5.6 5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . 56 Features . . . . . . . . . . . . . . . . . . . . . . . . . 56 Functional Description . . . . . . . . . . . . . . 56 Block Diagram. . . . . . . . . . . . . . . . . . . . . 59 Operating Modes . . . . . . . . . . . . . . . . . . 59 Register Descriptions . . . . . . . . . . . . . . . 59 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .149
11.1 56F8035/56F8025 Package and Pin-Out Information . . . . . . . . . . . 149
Part 6 System Integration Module (SIM) . . . 79
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . 79 Features . . . . . . . . . . . . . . . . . . . . . . . . . 80 Register Descriptions . . . . . . . . . . . . . . . 81 Clock Generation Overview . . . . . . . . . 106 Power-Saving Modes . . . . . . . . . . . . . . 108 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 112
Part 12Design Considerations . . . . . . . . . .155
12.1 12.2 Thermal Design Considerations . . . . . . 155 Electrical Design Considerations . . . . . 156
Part 13Ordering Information . . . . . . . . . . . .157 Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .158
Part 7 Security Features. . . . . . . . . . . . . . . 112
7.1 7.2 Operation with Security Enabled. . . . . . 112 Flash Access Lock and Unlock Mechanisms . . . . . . . . . . . . . . . . . 113 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 5
Part 1 Overview
1.1 56F8035/56F8025 Features
1.1.1
* * * * * * * * * * * * * *
Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent real-time debugging
1.1.2
Difference Between Devices
Table 1-1 Device Differences
On-Chip Memory Program Flash (PFLASH) Unified RAM (RAM) 56F8035 56F8025 64KB 8KB 32KB 4KB
Table 1-1 outlines the key differences between the 56F8033 and 56F8023 devices.
1.1.3
* * *
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal Flash On-chip memory -- 64KB of Program Flash (56F80235 device) 32KB of Program Flash (56F8025 device) -- 8KB of Unified Data/Program RAM (56F8035 device) 4KB of Unified Data/Program RAM (56F8025 device)
*
EEPROM emulation capability using Flash
56F8035/56F8025 Data Sheet, Rev. 6 6 Freescale Semiconductor
56F8035/56F8025 Features
1.1.4
*
Peripheral Circuits for 56F8035/56F8025
One multi-function six-output Pulse Width Modulator (PWM) module -- Up to 96MHz PWM operating clock -- 15 bits of resolution -- Center-aligned and edge-aligned PWM signal mode -- Four programmable fault inputs with programmable digital filter -- Double-buffered PWM registers -- Each complementary PWM signal pair allows selection of a PWM supply source from: - PWM generator - External GPIO - Internal timers - Analog comparator outputs - ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output
*
Two independent 12-bit Analog-to-Digital Converters (ADCs) -- 2 x 4 channel inputs -- Supports both simultaneous and sequential conversions -- ADC conversions can be synchronized by both PWM and timer modules -- Sampling rate up to 2.67MSPS -- 16-word result buffer registers
*
Two internal 12-bit Digital-to-Analog Converters (DACs) -- 2 microsecond settling time when output swing from rail to rail -- Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range
*
One 16-bit multi-purpose Quad Timer module (TMR) -- Up to 96MHz operating clock -- Eight independent 16-bit counter/timers with cascading capability -- Each timer has capture and compare capability -- Up to 12 operating modes
*
One Queued Serial Communication Interface (QSCI) with LIN Slave functionality -- Full-duplex or single-wire operation -- Two receiver wake-up methods: - Idle line - Address mark -- Four-bytes-deep FIFOs are available on both transmitter and receiver
*
One Queued Serial Peripheral Interfaces (QSPI)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 7
-- Full-duplex operation -- Master and slave modes -- Four-words-deep FIFOs available on both transmitter and receiver -- Programmable Length Transactions (2 to 16 bits) * One Inter-Integrated Circuit (I2C) port -- Operates up to 400kbps -- Supports both master and slave operation -- Supports both 10-bit address mode and broadcasting mode * * Three 16-bit Programmable Interval Timers (PITs) Two analog Comparators (CMPs) -- Selectable input source includes external pins, DACs -- Programmable output polarity -- Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs -- Output falling and rising edge detection able to generate interrupts * * * * * Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals Clock sources: -- On-chip relaxation oscillator -- External clock: Crystal oscillator, ceramic resonator, and external clock source * JTAG/EOnCE debug programming interface for real-time debugging
1.1.5
* * * * *
Energy Information
Fabricated in high-density CMOS with 5V tolerance On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power
1.2 56F8035/56F8025 Description
The 56F8035/56F8025 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8035/56F8025 is well-suited for many applications. The 56F8035/56F8025 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and
56F8035/56F8025 Data Sheet, Rev. 6 8 Freescale Semiconductor
Award-Winning Development Environment
security systems, switched-mode power supply, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8035/56F8025 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8035/56F8025 also offers up to 35 General-Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8035 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified Data/Program RAM. The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peripherals -- PWM, ADCs, QSCI, QSPI, I2C, PITs, Quad Timers, DACs, and analog comparators -- supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8035/56F8025's architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6, and 1-7 detail how the device's I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please see Part 2, Signal/Connection Descriptions, for information about which signals are multiplexed with those of other peripherals.
1.4.1
PWM, TMR and ADC Connections
Figure 1-6 shows the over-limit and under-limit connections from the ADC to the PWM and the connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 9
additional information. The PWM_reload_sync output can be connected to the Timer's Channel 3 input and the Timer's Channels 2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0 and Timer Channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register; see Section 6.3.1.
DSP56800E Core
Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) M01 N3 Looping Unit ALU1 ALU2
Instruction Decoder Interrupt Unit
R0 R1 R2 R3 R4 R5 N SP XAB1 XAB2 PAB PDB CDBW CDBR XDB2 Data / Program RAM Program Memory
BitManipulation Unit Y
A2 B2 C2 D2
Enhanced OnCETM
A1 B1 C1 D1 Y1 Y0 X0
A0 B0 C0 D0 Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter
IPBUS Interface
JTAG TAP
MAC and ALU
Figure 1-1 56800E Core Block Diagram
56F8035/56F8025 Data Sheet, Rev. 6 10 Freescale Semiconductor
Architecture Block Diagram
To/From IPBus Bridge
OCCS (ROSC / PLL / OSC)
Interrupt Controller Low-Voltage Interrupt
GPIO A
POR & LVI
GPIO B
System POR
GPIO C
SIM RESET (Muxed with GPIOA7)
GPIO D
COP Reset COP
IPBus (Continues on Figure 1-3)
Figure 1-2 Peripheral Subsystem
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 11
To/From IPBus Bridge
IPBus
INTC
SYNC PIT0 MSTR_CNT_EN 3 MSTR_CNT_EN PIT1 SYNC
DAC SYNC on Figure 1-5
MSTR_CNT_EN PIT2
SYNC
2 3 Sync0, Sync1 Over/Under Limits
SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA2 (VREFHA) ANA3 (VREFLA) ANA0 on Figure 1-5 GPIOC2 GPIOC3
ANA1
GPIOC1
ADC
ANB0 ANB2 (VREFHB) ANB3 (VREFLB)
ANB0 on Figure 1-5 GPIOC6 GPIOC7
ANB1
GPIOC5
Figure 1-3 56F8035/56F8025 I/O Pin-Out Muxing (Part 1/5)
56F8035/56F8025 Data Sheet, Rev. 6 12 Freescale Semiconductor
Architecture Block Diagram
To/From IPBus Bridge
GPIOB6 - 7 RXD0, TXD0 2 GPIOB2 - 3 MISO0, MOSI0 QSPI0 SCLK0, SS0 2 2 I2C SCL, SDA 2 2 GPIOB0 - 1 2
QSCI0
TA2, TA3 on Figure 1-7
IPBus
Figure 1-4 56F8035/56F8025 I/O Pin-Out Muxing (Part 2/5)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 13
To/From IPBus Bridge
FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMP_IN1 CMP_IN3 CMPA CMP_OUT CMP_IN2 Export Import CMPAO on Figure 1-6, Figure 1-7 CMPAI2 ANA0 on Figure 1-3 TB2 on Figure 1-4 GPIOB10 DAC0 GPIOA10 CMPAI1 CMPAI3 GPIOC0 GPIOA8
2 3
TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6
DAC1 GPIOB11
Import Export CMP_IN2 CMP_OUT CMPB CMP_IN3 CMP_IN1
ANB0 on Figure 1-3 CMPBI2 CMPBO on Figure 1-6, Figure 1-7 GPIOC4 CMPBI3 CMPBI1 TA3 on Figure 1-7 FAULT2 on Figure 1-6 GPIOA9 GPIOA11
IPBus
Figure 1-5 56F8035/56F8025 I/O Pin-Out Muxing (Part 3/5)
56F8035/56F8025 Data Sheet, Rev. 6 14 Freescale Semiconductor
Architecture Block Diagram
To/From IPBus Bridge
TA0 on Figure 1-7 TA2 - 3 on Figure 1-7 2
GPIOA6
PWM0 - 3 FAULT0 PWMA4 - 5
4
GPIOA0 - 3
2 1 2
GPIOA4 - 5
PWM FAULT1 FAULT1 on Figure 1-5
FAULT2 RELOAD PSRC0 - 1 FAULT3
1 FAULT2 on Figure 1-5
TA1 on Figure 1-7 GPIOB5 RELOAD on Figure 1-7, Figure 1-5
CMPAO on Figure 1-5 CMPBO on Figure 1-5
IPBus
3
3 3 3
GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3
Figure 1-6 56F8035/56F8025 I/O Pin-Out Muxing (Part 4/5)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 15
To/From IPBus Bridge
TA0o on Figure 1-6 (PWM)
T0o T0i
TA0 on Figure 1-6 (GPIOA6)
T1o T1i TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA)
TMRA
SYNC1 on Figure 1-3 (ADC) TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o T2i TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) T3o T3i TA3 on Figure 1-4 (GPIOB3) RELOAD on Figure 1-6 (PWM) TA3 on Figure 1-5 (GPIOA9) TA2 on Figure 1-5 (GPIOA8)
IPBus
Figure 1-7 56F8035/56F8025 I/O Pin-Out Muxing (Part 5/5)
56F8035/56F8025 Data Sheet, Rev. 6 16 Freescale Semiconductor
Product Documentation
1.5 Product Documentation
The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8035/56F8025. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8035/56F8025 Chip Documentation
Topic DSP56800E Reference Manual 56F802x and 56F803x Peripheral Reference Manual 56F802x and 56F803x Serial Bootloader User Guide 56F8035/56F8025 Technical Data Sheet 56F8035/56F8025 Errata Description Detailed description of the 56800E family architecture, 16-bit Digital Signal Controller core processor, and the instruction set Detailed description of peripherals of the 56F802x and 56F803x family of devices Detailed description of the Serial Bootloader in the 56F802x and 56F803x family of devices Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number DSP56800ERM
MC56F80xxRM
56F80xxBLUG
MC56F8035/56F8025 MC56F8035/56F8025E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 17
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8035/56F8025 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number. Table 2-1 Functional Group Pin Allocations
Functional Group Power Inputs (VDD, VDDA) Ground (VSS, VSSA) Supply Capacitors Reset1 Pulse Width Modulator (PWM) Ports1 Serial Peripheral Interface (SPI) Ports1 Timer Module A (TMRA) Ports1 Analog-to-Digital Converter (ADC) Ports1 Serial Communications Interface 0 (SCI0) Ports1 Inter-Integrated Circuit Interface (I2C) Ports1 Oscillator Signals1 JTAG/Enhanced On-Chip Emulation (EOnCE)1
1. Pins may be shared with other peripherals; see Table 2-2.
Number of Pins 3 4 2 1 12 4 4 8 2 2 2 4
56F8035/56F8025 Data Sheet, Rev. 6 18 Freescale Semiconductor
Introduction
In Table 2-2, peripheral pins in bold identify reset state. Table 2-2 56F8035/56F8025 Pins
Peripherals: Pin # 1 2 3 4 5 6 7 8 9 Pin Name GPIOB6 GPIOB1 GPIOB7 GPIOB5 GPIOA9 GPIOA11 GPIOC4 GPIOC5 GPIOC6 Signal Name GPIOB6, RXD0, SDA, CLKIN GPIOB1, SS0, SDA GPIOB7, TXD0, SCL GPIOB5, TA1, FAULT3, CLKIN GPIOA9, FAULT2, TA3, CMPBI1 GPIOA11, CMPBI2 GPIOC4, ANB0, CMPBI3 GPIOC5, ANB1 GPIOC6, ANB2, VREFHB GPIOC7, ANB3, VREFLB VDDA VSSA GPIOC3, ANA3, VREFLA GPIOC2, ANA2, VREFHA GPIOC1, ANA1 GPIOC0, ANA0, CMPAI3 VSS VCAP TCK, GPIOD2 GPIOB10, CMPAO RESET, GPIOA7 GPIOB3, MOSI0, TA3, PSRC1 GPIOB2, MISO0, TA2, PSRC0 GPIOA6, FAULT0, TA0 GPIOA10, CMPAI2 GPIOA8, FAULT1, TA2, CMPAI1 GPIOA5, PWM5, TA3, FAULT2 D2 B10 A7 B3 B2 A6 A10 A8 A5 FAULT1 PWM5 FAULT2 TA2 TA3 MOSI0 MISO0 PSRC1 PSRC0 FAULT0 TA3 TA2 TA0 CMPAI2 CMPAI1 CMPAO RESET C3 ANA3 VREFLA ANA2 VREFHA ANA1 ANA0 CMPAI3 VSS VCAP TCK GPIO B6 B1 B7 B5 A9 A11 C4 C5 C6 ANB0 ANB1 ANB2 VREFHB ANB3 VREFLB VDDA VSSA I2C SDA SDA SCL TXD0 FAULT3 FAULT2 TA1 TA3 CMPBI1 CMPBI2 CMPBI3 CLKIN QSCI RXD0 SS0 QSPI ADC PWM Quad Timer Comp Power & Ground JTAG Misc CLKIN
10
GPIOC7
C7
11 12 13
VDDA VSSA GPIOC3
14
GPIOC2
C2
15 16 17 18 19 20 21 22 23 24 25 26 27
GPIOC1 GPIOC0 VSS_IO VCAP TCK GPIOB10 RESET GPIOB3 GPIOB2 GPIOA6 GPIOA10 GPIOA8 GPIOA5
C1 C0
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 19
Table 2-2 56F8035/56F8025 Pins (Continued)
Peripherals: Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name VSS_IO VDD_IO GPIOB0 GPIOA4 GPIOA2 GPIOA3 VCAP VDD_IO VSS_IO GPIOD5 GPIOD4 GPIOA1 GPIOA0 TDI GPIOB11 TMS TDO VSS VDD GPIOB0, SCLK0, SCL GPIOA4, PWM4, TA2, FAULT1 GPIOA2, PWM2 GPIOA3, PWM3 VCAP VDD VSS GPIOD5, XTAL, CLKIN GPIOD4, EXTAL GPIOA1, PWM1 GPIOA0, PWM0 TDI, GPIOD0 GPIOB11, CMPBO TMS, GPIOD3 TDO, GPIOD1 D5 D4 A1 A0 D0 B11 D3 D1 CMPBO TMS TDO PWM1 PWM0 TD1 B0 A4 A2 A3 SCL SCLK0 PWM4 FAULT1 PWM2 PWM3 VCAP VDD VSS XTAL CLKIN EXTAL TA2 Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer Comp Power & Ground VSS VDD JTAG Misc
56F8035/56F8025 Data Sheet, Rev. 6 20 Freescale Semiconductor
Introduction
Power Ground Power Ground Other Supply Ports OSC Port or GPIO
VDD VSS VDDA VSSA 2 3 1 1 4 1
GPIOA0-3 (PWM0-3) GPIOA4 (PWM4, TA2, FAULT1) GPIOA5 (PWM5, TA3, FAULT2)
1 GPIOA6 (FAULT0, TA0) 1 GPIOA8 (FAULT1, TA2, CMPAI1) GPIOA9 (FAULT2, TA3, CMPBI1) 1 GPIOA10 (CMPAI2) 1 GPIOA11 (CMPBI2) 1
VCAP GPIOD4 (EXTAL)
56F8035/56F802 1
2 1
PWM or TMRA or CMP or GPIOA
GPIOD5 (XTAL, CLKIN) 1
RESET or GPIOA
RESET (GPIOA7) 1 GPIOB0 (SCLK0, SCL)
QSPI or I2C or PWM or TMRA or GPIOB
1 GPIOB1 (SS0, SDA) 1 GPIOB2 (MISO0, TA2, PSRC0) 1 GPIOB3 (MOSI0, TA3, PSRC1) 1 1 1 GPIOB11 (CMPBO) GPIOB10 (CMPAO) CMP or GPIOB
QSCI or PWM or I2C or TMRA or QSPI or GPIOB
GPIOB5 (TA1, FAULT3, CLKIN) 1 GPIOB6 (RXD0, SDA, CLKIN) GPIOB7 (TXD0, SCL) 1 1 1 1 1 GPIOC2 (ANA2, VREFHA) GPIOC3 (ANA3, VREFLA) ADC or CMP or GPIOC GPIOC4 (ANB0 & CMPBI3) 1 TDO (GPIOD1) 1 GPIOC5 (ANB1) 1 1 TCK (GPIOD2) 1 TMS (GPIOD3) 1 1 1 GPIOC6 (ANB2, VREFHA) GPIOC7 (ANB3, VREFLB) GPIOC0 (ANA0 & CMPAI3) 1 GPIOC1 (ANA1)
TDI (GPIOD0)
JTAG/ EOnCE or GPIOD
Figure 2-1 56F8035/56F8025 Signals Identified by Functional Group
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 21
2.2 56F8035/56F8025 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name VDD VDD VSS VSS VSS VDDA LQFP Pin No. 29 35 17 28 36 11 Supply Supply ADC Power -- This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. ADC Analog Ground -- This pin supplies an analog ground to the ADC modules. VCAP -- Connect this pin to a 2.2F or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. See Section 10.2.1. Reset -- This input is a direct hardware reset on the processor. When RESET is asserted low, the chip is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. Port A GPIO -- This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. Supply Supply VSS -- These pins provide ground for chip logic and I/O drivers. Type Supply State During Reset Supply Signal Description I/O Power -- This pin supplies 3.3V power to the chip I/O interface.
VSSA
12
Supply
Supply
VCAP VCAP RESET
18 34 21
Supply
Supply
Input
Input, internal pull-up enabled
(GPIOA7)
Input/Open Drain Output
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 22 Freescale Semiconductor
56F8035/56F8025 Signal Pins
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOA0 LQFP Pin No. 40 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM0)
Output
PWM0 -- This is one of the six PWM output pins. After reset, the default state is GPIOA0.
GPIOA1
39
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM1)
Output
PWM1 -- This is one of the six PWM output pins. After reset, the default state is GPIOA1.
GPIOA2
32
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM2)
Output
PWM2 -- This is one of the six PWM output pins. After reset, the default state is GPIOA2.
GPIOA3
33
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM3)
Output
PWM3 -- This is one of the six PWM output pins. After reset, the default state is GPIOA3.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 23
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOA4 LQFP Pin No. 31 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM4) (TA21) (FAULT12)
Output Input/ Output Input
PWM4 -- This is one of the six PWM output pins. TA2 -- Timer A, Channel 2
Fault1 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA4. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
1The 2
TA2 signal is also brought out on the GPIOA8-9 and GPIOB2-3 pins.
The Fault1 signal is also brought out on the GPIOA8-9 and GPIOB10 pins.
GPIOA5
27
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(PWM5) (TA33)
Output Input/ Output Input
PWM5 -- This is one of the six PWM output pins. TA3 -- Timer A, Channel 3
(FAULT24)
Fault2 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip.
After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
3
The TA3 signal is also brought out on the GPIOA8-9 and GPIOB2-3 pins. Fault2 signal is also brought out on the GPIOA8-9 and GPIOB10 pins.
4The
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 24 Freescale Semiconductor
56F8035/56F8025 Signal Pins
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOA6 LQFP Pin No. 24 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(FAULT0)
Input
Fault0 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 -- Timer A, Channel 0. After reset, the default state is GPIOA6. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
(TA0)
GPIOA8
26
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(FAULT1)
Input
Fault1 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 -- Timer A, Channel 2.
(TA2)
Input/ Output Input
(CMPAI1)
Comparator A, Input 1 -- This is an analog input to Comparator A. After reset, the default state is GPIOA8. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
GPIOA9
5
Input/ Output
Input, internal pull-up enabled
Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(FAULT2)
Input
Fault2 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 -- Timer A, Channel 3.
(TA3)
Input/ Output Input
(CMPBI1)
Comparator B, Input 1 -- This is an analog input to Comparator B. After reset, the default state is GPIOA9. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 25
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOA10 LQFP Pin No. 25 Type Input/ Output Input State During Reset Input, internal pull-up enabled Signal Description Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. Comparator A, Input 2 -- This is an analog input to Comparator A. After reset, the default state is GPIOA10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOA11 6 Input/ Output Input Input, internal pull-up enabled Port A GPIO -- This GPIO pin can be individually programmed as an input or output pin. Comparator B, Input 2 -- This is an analog input to Comparator B. After reset, the default state is GPIOA11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOB0 30 Input/ Output Input, internal pull-up enabled Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(CMPAI2)
(CMPBI2)
(SCLK0)
Input/ Output
QSPI0 Serial Clock -- In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. Serial Clock -- This pin serves as the I2C serial clock. After reset, the default state is GPIOB0. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
(SCL5)
Input/ Output
5The
SCL signal is also brought out on the GPIOB7 pin.
GPIOB1
2
Input/ Output
Input, internal pull-up enabled
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. QSPI0 Slave Select -- SS is used in slave mode to indicate to the QSPI0 module that the current transfer is to be received. Serial Data -- This pin serves as the I2C serial data line.
(SS0)
Input/ Output Input
(SDA6)
After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
6The
SDA signal is also brought out on the GPIOB6 pin.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 26 Freescale Semiconductor
56F8035/56F8025 Signal Pins
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOB2 LQFP Pin No. 23 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(MISO0)
Input/ Output
QSPI0 Master In/Slave Out -- This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. TA2 -- Timer A, Channel 2
(TA27)
Input/ Output Input
(PSRC0)
PSRC0 -- External PWM signal source input for the complementary PWM4/PWM5 pair. After reset, the default state is GPIOB2. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
7
The TA2 signal is also brought out on the GPIOA4 and GPIOA8 pins.
GPIOB3
22
Input/ Output
Input, internal pull-up enabled
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(MOSI0)
Input/ Output
QSPI0 Master Out/Slave In-- This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. TA3 -- Timer A, Channel 3
(TA38)
Input/ Output Input
(PSRC1)
PSRC1 -- External PWM signal source input for the complementary PWM2/PWM3 pair. After reset, the default state is GPIOB3. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
8
The TA3 signal is also brought out on the GPIOA5 and GPIOA9 pins.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 27
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOB5 LQFP Pin No. 4 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(TA1)
Input/ Output Input
TA1 -- Timer A, Channel 1
(FAULT3)
FAULT3 -- This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. External Clock Input-- This pin serves as an external clock input. After reset, the default state is GPIOB5. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
(CLKIN)
Input
GPIOB6
1
Input/ Output
Input, internal pull-up enabled
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin.
(RXD0) (SDA9)
Input Input/ Output Input
Receive Data 0 -- QSCI0 receive data input. Serial Data -- This pin serves as the I2C serial data line.
(CLKIN)
External Clock Input -- This pin serves as an external clock input. After reset, the default state is GPIOB6. The peripheral functionality is controlled via the SIM (See Section 6.3.16) and the CLKMODE bit of the OCCS Oscillator Control Register.
9
The SDA signal is also brought out on the GPIOB1 pin.
GPIOB7
3
Input/ Output
Input, internal pull-up enabled
Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. Transmit Data 0 -- QSCI0 transmit data output or transmit/receive in single wire operation. Serial Clock -- This pin serves as the I2C serial clock.
(TXD0)
Input/ Output Input/ Output
(SCL10)
After reset, the default state is GPIOB7. The peripheral functionality is controlled via the SIM. See Section 6.3.16.
10The
SCL signal is also brought out on the GPIOB0 pin.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 28 Freescale Semiconductor
56F8035/56F8025 Signal Pins
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOB10 LQFP Pin No. 20 Type Input/ Output Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. Comparator A Output-- This is the output of comparator A. After reset, the default state is GPIOB10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOB11 42 Input/ Output Output Input, internal pull-up enabled Port B GPIO -- This GPIO pin can be individually programmed as an input or output pin. Comparator B Output-- This is the output of comparator B. After reset, the default state is GPIOB11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOC0 16 Input/ Output Analog Input Input Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANA0 -- Analog input to ADC A, Channel 0. Comparator A, Input 3 -- This is an analog input to Comparator A. When used as an analog input, the signal goes to both the ANA0 and CMPAI3. After reset, the default state is GPIOC0. GPIOC1 15 Input/ Output Analog Input Input Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANA1 -- Analog input to ADC A, Channel 1. After reset, the default state is GPIOC1. GPIOC2 14 Input/ Output Analog Input Analog Input Input Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANA2 -- Analog input to ADC A, Channel 2.
(CMPAO)
(CMPBO)
(ANA0 & CMPAI3)
(ANA1)
(ANA2)
(VREFHA)
VREFHA -- Analog reference voltage high (ADC A). After reset, the default state is GPIOC2.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 29
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOC3 LQFP Pin No. 13 Type Input/ Output Analog Input Analog Input State During Reset Input Signal Description Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANA3 -- Analog input to ADC A, Channel 3.
(ANA3)
(VREFLA)
VREFLA -- Analog reference voltage low (ADC A). After reset, the default state is GPIOC3.
GPIOC4
7
Input/ Output Analog Input
Input
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANB0 -- Analog input to ADC B, Channel 0. Comparator B, Input 3 -- This is an analog input to Comparator B. When used as an analog input, the signal goes to both the ANB0 and CMPBI3. After reset, the default state is GPIOC4.
(ANB0 & CMPBI3)
GPIOC5
8
Input/ Output Analog Input
Input
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANB1 -- Analog input to ADC B, Channel 1. After reset, the default state is GPIOC5.
(ANB1)
GPIOC6
9
Input/ Output Analog Input Input
Input
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANB2 -- Analog input to ADC B, Channel 2.
(ANB2)
(VREFHB)
VREFHB -- Analog reference voltage high (ADC B). After reset, the default state is GPIOC6.
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 30 Freescale Semiconductor
56F8035/56F8025 Signal Pins
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name GPIOC7 LQFP Pin No. 10 Type Input/ Output Analog Input Input State During Reset Input Signal Description Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. ANB3 -- Analog input to ADC B, Channel 3.
(ANB3)
(VREFLB)
VREFLB -- Analog reference voltage low (ADC B). After reset, the default state is GPIOC7.
GPIOD4
38
Input/ Output Analog Input
Input
Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Input -- This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is being driven by an external clock source. After reset, the default state is GPIOD4.
(EXTAL)
GPIOD5
37
Input/ Output Analog Input/ Output Input
Input
Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Output -- This output connects the internal crystal oscillator output to an external crystal.
(XTAL)
(CLKIN)
External Clock Input -- This pin serves as an external clock input. After reset, the default state is GPIOD5.
TDI
41
Input
Input, internal pull-up enabled
Test Data Input -- This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI.
(GPIOD0)
Input/ Output
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 31
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal Name TDO LQFP Pin No. 44 Type Output State During Reset Output tri-stated, internal pull-up enabled Signal Description Test Data Output -- This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. TCK 19 Input Input, internal pull-up enabled Test Clock Input -- This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. TMS 43 Input Input, internal pull-up enabled Test Mode Select Input -- This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to VDD through a 2.2K resistor.
(GPIOD1)
Input/ Output
(GPIOD2)
Input/ Output
(GPIOD3)
Input/ Output
Return to Table 2-2
56F8035/56F8025 Data Sheet, Rev. 6 32 Freescale Semiconductor
Overview
Part 3 OCCS
3.1 Overview
The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual.
3.2 Features
The OCCS module interfaces to the oscillator and PLL and offers these features:
* * * * * * * * * Internal relaxation oscillator Ability to power down the internal relaxation oscillator or crystal oscillator Ability to put the internal relaxation oscillator into Standby mode 3-bit postscaler provides control for the PLL output Ability to power down the PLL Provides a 2X system clock which operates at twice the system clock to the System Integration Module (SIM) Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules Safety shutdown feature is available if the PLL reference clock is lost Can be driven from an external clock source
The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator.
3.3 Operating Modes
In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be used to provide a reference clock to the SIM. The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency x 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 33
The 56F8000 family devices' on-chip clock synthesis module has the following registers:
* * * * * Control Register (OCCS_CTRL) Divide-by Register (OCCS_DIVBY) Status Register (OCCS_STAT) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL)
For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference Manual.
3.4 Internal Clock Source
An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations which accommodate different operating conditions. The internal relaxation oscillator has very little temperature and voltage variability. To optimize power, the architecture supports a standby state and a power-down state. During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a changeover between internal and external clock sources is required at power-on, the user must ensure that the clock source is not switched until the desired external clock source is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved. The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the 56F802x and 56F803x Peripheral Reference Manual.
3.5 Crystal Oscillator
The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator circuit. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
56F8035/56F8025 Data Sheet, Rev. 6 34 Freescale Semiconductor
Ceramic Resonator
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL Rz
EXTAL XTAL Rz
Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg
CL1
CL2
Figure 3-1 External Crystal Oscillator Circuit
3.6 Ceramic Resonator
The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz. Figure 3-2 shows the typical 2- and 3-terminal ceramic resonators and their circuits. Follow the resonator supplier's recommendations when selecting a resonator, since their parameters determine the component values required to provide maximum stability and reliable start up. The load capacitance values used in the resonator circuit design should include all stray layout capacitances. The resonator and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal 3 Terminal
EXTAL XTAL Rz
EXTAL XTAL Rz
Sample External Ceramic Resonator Parameters: Rz = 750 K
CL1
CL2
C1
C2
Figure 3-2 External Ceramic Resonator Circuit
3.7 External Clock Input - Crystal Oscillator Option
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 35
56F8035/56F8025 CLKMODE = 1 XTAL External Clock EXTAL GND or GPIO
Figure 3-3 Connecting an External Clock Signal using XTAL
3.8 Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input.
56F8035/56F8025 GPIO External Clock
Figure 3-4 Connecting an External Clock Signal using GPIO
Part 4 Memory Maps
4.1 Introduction
The 56F8035/56F8025 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both spaces and Flash memory is used only in Program space. This section provides memory maps for:
* * Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories' restrictions are identified in the "Use Restrictions" column of Table 4-1.
56F8035/56F8025 Data Sheet, Rev. 6 36 Freescale Semiconductor
Interrupt Vector Table
Table 4-1 Chip Memory Configurations
On-Chip Memory Program Flash (PFLASH) Unified RAM (RAM) 56F8035 56F8025 32K x 16 16K x 16 or 64KB or 32KB 4K x 16 or 8KB 2K x 16 or 4KB Use Restrictions Erase/Program via Flash interface unit and word writes to CDBW Usable by both the Program and Data memory spaces
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8035/56F8025's reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8 for the reset value of the VBA. By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Table 4-2 Interrupt Vector Table Contents1
Peripheral core core core core core core core core core core core core core core LVI PLL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1-3 1-3 P:$1E P:$20 3 3 3 3 1-3 1-3 1-3 1-3 1-3 2 1 0 Vector Number Priority Level Vector Base Address + P:$00 P:$02 P:$04 P:$06 P:$08 P:$0A P:$0C P:$0E P:$10 P:$12 P:$14 P:$16 P:$18 P:$1A Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access EOnCE Step Counter EOnCE Breakpoint Unit EOnCE Trace Buffer EOnCE Transmit Register Empty EOnCE Receive Register Full SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 Reserved Low-Voltage Detector (Power Sense) Phase-Locked Loop
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 37
Table 4-2 Interrupt Vector Table Contents1 (Continued)
Peripheral FM FM FM GPIOD GPIOC GPIOB GPIOA QSPI0 QSPI0 QSCI0 QSCI0 QSCI0 QSCI0 I2C I2C I2C I2C I2C TMRA TMRA TMRA TMRA CMPA CMPB PIT0 PIT1 PIT2 ADC ADC ADC PWM PWM SWILP Vector Number 17 18 19 20-23 24 25 26 27 28 29 30-31 32 33 34 35 36-39 40 41 42 43 44 45 46 47 48 49-52 53 54 55 56 57 58 59 60 61 62 63 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 -1 P:$6A P:$6C P:$6E P:$70 P:$72 P:$74 P:$76 P:$78 P:$7A P:$7C P:$7E 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 P:$50 P:$52 P:$54 P:$56 P:$58 P:$5A P:$5C P:$5E P:$60 0-2 0-2 0-2 0-2 P:$40 P:$42 P:$44 P:$46 0-2 0-2 0-2 0-2 0-2 0-2 P:$30 P:$32 P:$34 P:$36 P:$38 P:$3A Priority Level 0-2 0-2 0-2 Vector Base Address + P:$22 P:$24 P:$26 Interrupt Function FM Access Error Interrupt FM Command Complete FM Command, Data, and Address Buffers Empty Reserved GPIOD GPIOC GPIOB GPIOA QSPI0 Receiver Full QSPI0 Transmitter Empty Reserved QSCI0 Transmitter Empty QSCI0 Transmitter Idle QSCI0 Receiver Error QSCI0 Receiver Full Reserved I2C Error I2C General I2C Receive I2C Transmit I2C Status Timer A, Channel 0 Timer A, Channel 1 Timer A, Channel 2 Timer A, Channel 3 Reserved Comparator A Comparator B Interval Timer 0 Interval Timer 1 Interval Timer 2 ADC A Conversion Complete ADC B Conversion Complete ADC Zero Crossing or Limit Error Reload PWM PWM Fault SW Interrupt Low Priority
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses since the reset address would match the base of this vector table.
56F8035/56F8025 Data Sheet, Rev. 6 38 Freescale Semiconductor
Program Map
4.3 Program Map
The Program Memory map is shown in Table 4-3 and Table 4-4. Table 4-3 Program Memory Map1 at Reset for 56F8035
Begin/End Address P: $1F FFFF P: $00 9000 P: $00 8FFF P: $00 8000 P: $00 7FFF P: $00 0000 RESERVED On-Chip RAM2 8KB Internal Program Flash 64KB Cop Reset Address = $00 0002 Boot Location = $00 0000 Memory Allocation
1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.
Table 4-4 Program Memory Map1 at Reset for 56F8025
Begin/End Address P: $1F FFFF P: $00 8800 P: $00 87FF P: $00 8000 P: $00 7FFF P: $00 4000 RESERVED On-Chip RAM2 4KB Internal Program Flash 32KB Cop Reset Address = $00 4002 Boot Location = $00 4000 RESERVED Memory Allocation
P: $00 3FFF P: $00 0000
1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-2.
4.4 Data Map
Table 4-5 Data Memory Map1 for 56F8035
Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 Memory Allocation EOnCE 256 locations allocated RESERVED
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 39
Table 4-5 Data Memory Map1 for 56F8035 (Continued)
Begin/End Address X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 8800 X:$00 87FF X:$00 8000 X:$00 7FFF X:$00 1000 X:$00 0FFF X:$00 0000 Memory Allocation On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED On-Chip Data RAM 8KB2
1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1.
Table 4-6 Data Memory Map1 for 56F8025
Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 8800 X:$00 87FF X:$00 8000 X:$00 7FFF X:$00 0800 X:$00 07FF X:$00 0000 Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED On-Chip Data RAM2 4KB
1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-2.
56F8035/56F8025 Data Sheet, Rev. 6 40 Freescale Semiconductor
EOnCE Memory Map
Program Reserved
Data EOnCE Reserved
RAM Peripherals Dual Port RAM Flash Reserved RAM
Figure 4-1 Dual Port RAM for 56F8035
Program Reserved
Data EOnCE Reserved
RAM Peripherals Flash Dual Port RAM Reserved Reserved RAM
Figure 4-2 Dual Port RAM for 56F8025
4.5 EOnCE Memory Map
Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-7 EOnCE Memory Map
Address X:$FF FFFF X:$FF FFFE X:$FF FFFD X:$FF FFFC Register Acronym OTX1 / ORX1 OTX / ORX (32 bits) OTXRXSR OCLSR Register Name Transmit Register Upper Word Receive Register Upper Word Transmit Register Receive Register Transmit and Receive Status and Control Register Core Lock / Unlock Status Register
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 41
Table 4-7 EOnCE Memory Map (Continued)
Address X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 X:$FF FF9F X:$FF FF9E X:$FF FF9D X:$FF FF9C X:$FF FF9B X:$FF FF9A X:$FF FF99 X:$FF FF98 X:$FF FF97 X:$FF FF96 X:$FF FF95 X:$FF FF94 X:$FF FF93 X:$FF FF92 X:$FF FF91 X:$FF FF90 X:$FF FF8F X:$FF FF8E X:$FF FF8D X:$FF FF8C X:$FF FF8B X:$FF FF8A X:$FF FF89 - X:$FF FF00 OESCR OBCNTR OBMSK (32 bits) OBAR2 (32 bits) OBAR1 (24 bits) OBCR (24 bits) OSCNTR (24 bits) OSR OBASE OTBCR OTBPR OCR Register Acronym Reserved Control Register Instruction Step Counter Instruction Step Counter Status Register Peripheral Base Address Register Trace Buffer Control Register Trace Buffer Pointer Register Trace Buffer Register Stages OTB (21 - 24 bits/stage) Trace Buffer Register Stages Breakpoint Unit Control Register Breakpoint Unit Control Register Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 2 Breakpoint Unit Address Register 2 Breakpoint Unit Mask Register 2 Breakpoint Unit Mask Register 2 Reserved EOnCE Breakpoint Unit Counter Reserved Reserved Reserved External Signal Control Register Reserved Register Name
4.6 Peripheral Memory-Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read or written using word accesses only. Table 4-8 summarizes base addresses for the set of peripherals on the 56F8035/56F8025 device. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-8 Data Memory Peripheral Base Address Map Summary
Peripheral Timer A TMRA Prefix Base Address X:$00 F000 Table Number 4-9
56F8035/56F8025 Data Sheet, Rev. 6 42 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral ADC PWM ITCN SIM COP CLK, PLL, OSC Power Supervisor GPIO Port A GPIO Port B GPIO Port C GPIO Port D PIT 0 PIT 1 PIT 2 DAC 0 DAC 1 Comparator A Comparator B QSCI 0 QSPI 0 I
2C
Prefix ADC PWM ITCN SIM COP OCCS PS GPIOA GPIOB GPIOC GPIOD PIT0 PIT1 PIT2 DAC0 DAC1 CMPA CMPB SCI0 SPI0 I2C FM
Base Address X:$00 F080 X:$00 F0C0 X:$00 F0E0 X:$00 F100 X:$00 F120 X:$00 F130 X:$00 F140 X:$00 F150 X:$00 F160 X:$00 F170 X:$00 F180 X:$00 F190 X:$00 F1A0 X:$00 F1B0 X:$00 F1C0 X:$00 F1D0 X:$00 F1E0 X:$00 F1F0 X:$00 F200 X:$00 F220 X:$00 F280 X:$00 F400
Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31
FM
Table 4-9 Quad Timer A Registers Address Map (TMRA_BASE = $00 F000)
Register Acronym TMRA0_COMP1 TMRA0_COMP2 TMRA0_CAPT TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCTRL TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_CSCTRL TMRA0_FILT Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Input Filter Register Reserved 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 43
Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000)
Register Acronym TMRA0_ENBL TMRA1_COMP1 TMRA1_COMP2 TMRA1_CAPT TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCTRL TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_CSCTRL TMRA1_FILT Address Offset $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B Register Description Timer Channel Enable Register Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Input Filter Register Reserved TMRA2_COMP1 TMRA2_COMP2 TMRA2_CAPT TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCTRL TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_CSCTRL TMRA2_FILT $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Input Filter Register Reserved TMRA3_COMP1 TMRA3_COMP2 TMRA3_CAPT TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCTRL TMRA3_CMPLD1 TMRA3_CMPLD2 $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2
56F8035/56F8025 Data Sheet, Rev. 6 44 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000)
Register Acronym TMRA3_CSCTRL TMRA3_FILT Address Offset $3A $3B Register Description Comparator Status and Control Register Input Filter Register Reserved
Table 4-10 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080)
Register Acronym ADC_CTRL1 ADC_CTRL2 ADC_ZXCTRL ADC_CLIST 1 ADC_CLIST 2 ADC_CLIST 3 ADC_CLIST 4 ADC_SDIS ADC_STAT ADC_RDY ADC_LIMSTAT ADC_ZXSTAT ADC_RSLT0 ADC_RSLT1 ADC_RSLT2 ADC_RSLT3 ADC_RSLT4 ADC_RSLT5 ADC_RSLT6 ADC_RSLT7 ADC_RSLT8 ADC_RSLT9 ADC_RSLT10 ADC_RSLT11 ADC_RSLT12 ADC_RSLT13 ADC_RSLT14 ADC_RSLT15 ADC_LOLIM0 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Channel List Register 3 Channel List Register 4 Sample Disable Register Status Register Conversion Ready Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Result Register 8 Result Register 9 Result Register 10 Result Register 11 Result Register 12 Result Register 13 Result Register 14 Result Register 15 Low Limit Register 0
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 45
Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080)
Register Acronym ADC_LOLIM1 ADC_LOLIM2 ADC_LOLIM3 ADC_LOLIM4 ADC_LOLIM5 ADC_LOLIM6 ADC_LOLIM7 ADC_HILIM0 ADC_HILIM1 ADC_HILIM2 ADC_HILIM3 ADC_HILIM4 ADC_HILIM5 ADC_HILIM6 ADC_HILIM7 ADC_OFFST0 ADC_OFFST1 ADC_OFFST2 ADC_OFFST3 ADC_OFFST4 ADC_OFFST5 ADC_OFFST6 ADC_OFFST7 ADC_PWR ADC_CAL Address Offset $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 Register Description Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4 Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3 High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register Calibration Register Reserved
Table 4-11 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F0C0)
Register Acronym PWM_CTRL PWM_FCTRL PWM_FLTACK PWM_OUT PWM_CNTR PWM_CMOD PWM_VAL0 Address Offset $0 $1 $2 $3 $4 $5 $6 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Register Description
56F8035/56F8025 Data Sheet, Rev. 6 46 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-11 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0)
Register Acronym PWM_VAL1 PWM_VAL2 PWM_VAL3 PWM_VAL4 PWM_VAL5 PWM_DTIM0 PWM_DTIM1 PWM_DMAP1 PWM_DMAP2 PWM_CNFG PWM_CCTRL PWM_PORT PWM_ICCTRL PWM_SCTRL PWM_SYNC PWM_FFILT0 PWM_FFILT1 PWM_FFILT2 PWM_FFILT3 Address Offset $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register 0 Dead Time Register 1 Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register Internal Correction Control Register Source Control Register Synchronization Window Register Fault0 Filter Register Fault1 Filter Register Fault2 Filter Register Fault3 Filter Register Register Description
Table 4-12 Interrupt Control Registers Address Map (ITCN_BASE = $00 F0E0)
Register Acronym ITCN_IPR0 ITCN_IPR1 ITCN_IPR2 ITCN_IPR3 ITCN_IPR4 ITCN_IPR5 ITCN_IPR6 ITCN_VBA ITCN_FIM0 ITCN_FIVAL0 ITCN_FIVAH0 ITCN_FIM1 ITCN_FIVAL1 ITCN_FIVAH1 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Register Description Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Vector Base Address Register Fast Interrupt Match 0 Register Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register Fast Interrupt Match 1 Register Fast Interrupt Vector Address Low 1 Register Fast Interrupt Vector Address High 1 Register
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 47
Table 4-12 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F0E0)
Register Acronym ITCN_IRQP0 ITCN_IRQP1 ITCN_IRQP2 ITCN_IRQP3 Address Offset $E $F $10 $11 Register Description IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 Reserved ITCN_ICTRL $16 Interrupt Control Register Reserved
Table 4-13 SIM Registers Address Map (SIM_BASE = $00 F100)
Register Acronym SIM_CTRL SIM_RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half JTAG ID Least Significant Half JTAG ID Power Control Register Reserved SIM_CLKOUT SIM_PCR SIM_PCE0 SIM_PCE1 SIM_SD0 SIM_SD1 SIM_IOSAHI SIM_IOSALO SIM_PROT SIM_GPSA0 SIM_GPSA1 SIM_GPSB0 SIM_GPSB1 SIM_GPSCD SIM_IPS0 SIM_IPS1 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 Clock Out Select Register Peripheral Clock Rate Register Peripheral Clock Enable Register 0 Peripheral Clock Enable Register 1 Peripheral STOP Disable Register 0 Peripheral STOP Disable Register 1 I/O Short Address Location High Register I/O Short Address Location Low Register Protection Register GPIO Peripheral Select Register 0 for GPIOA GPIO Peripheral Select Register 1 for GPIOA GPIO Peripheral Select Register 0 for GPIOB GPIO Peripheral Select Register 1 for GPIOB GPIO Peripheral Select Register for GPIOC and GPIOD Internal Peripheral Source Select Register 0 for PWM Internal Peripheral Source Select Register 1 for DACs Register Description
56F8035/56F8025 Data Sheet, Rev. 6 48 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-13 SIM Registers Address Map (Continued) (SIM_BASE = $00 F100)
Register Acronym SIM_IPS2 Address Offset $1A Register Description Internal Peripheral Source Select Register 2 for TMRA Reserved
Table 4-14 Computer Operating Properly Registers Address Map (COP_BASE = $00 F120)
Register Acronym COP_CTRL COP_TOUT COP_CNTR Address Offset $0 $1 $2 Control Register Time-Out Register Counter Register Register Description
Table 4-15 Clock Generation Module Registers Address Map (OCCS_BASE = $00 F130)
Register Acronym OCCS_CTRL OCCS_DIVBY OCCS_STAT Address Offset $0 $1 $2 Control Register Divide-By Register Status Register Reserved OCCS_OCTRL OCCS_CLKCHK OCCS_PROT $5 $6 $7 Oscillator Control Register Clock Check Register Protection Register Register Description
Table 4-16 Power Supervisor Registers Address Map (PS_BASE = $00 F140)
Register Acronym PS_CTRL PS_STAT Address Offset $0 $1 Control Register Status Register Reserved Register Description
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 49
Table 4-17 GPIOA Registers Address Map (GPIOA_BASE = $00 F150)
Register Acronym GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Input Register Output Drive Strength Control Register
Table 4-18 GPIOB Registers Address Map (GPIOB_BASE = $00 F160)
Register Acronym GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Input Register Output Drive Strength Control Register
Table 4-19 GPIOC Registers Address Map (GPIOC_BASE = $00 F170)
Register Acronym GPIOC_PUPEN Address Offset $0 Register Description Pull-up Enable Register
56F8035/56F8025 Data Sheet, Rev. 6 50 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-19 GPIOC Registers Address Map (GPIOC_BASE = $00 F170)
Register Acronym GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Address Offset $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Input Register Output Drive Strength Control Register
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 51
Table 4-20 GPIOD Registers Address Map (GPIOD_BASE = $00 F180)
Register Acronym GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Edge Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Output Mode Control Register Raw Data Input Register Output Drive Strength Control Register
Table 4-21 Programmable Interval Timer 0 Registers Address Map (PIT0_BASE = $00 F190)
Register Acronym PIT0_CTRL PIT0_MOD PIT0_CNTR Address Offset $0 $1 $2 Control Register Modulo Register Counter Register Register Description
Table 4-22 Programmable Interval Timer 1 Registers Address Map (PIT1_BASE = $00 F1A0)
Register Acronym PIT1_CTRL PIT1_MOD PIT1_CNTR Address Offset $0 $1 $2 Control Register Modulo Register Counter Register Register Description
Table 4-23 Programmable Interval Timer 2 Registers Address Map (PIT2_BASE = $00 F1B0)
Register Acronym PIT2_CTRL Address Offset $0 Control Register Register Description
56F8035/56F8025 Data Sheet, Rev. 6 52 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-23 Programmable Interval Timer 2 Registers Address Map (Continued) (PIT2_BASE = $00 F1B0)
Register Acronym PIT2_MOD PIT2_CNTR Address Offset $1 $2 Modulo Register Counter Register Register Description
Table 4-24 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0)
Register Acronym DAC0_CTRL DAC0_DATA DAC0_STEP DAC0_MINVAL DAC0_MAXVAL Address Offset $0 $1 $2 $3 $4 Control Register Data Register Step Register Minimum Value Register Maximum Value Register Register Description
Table 4-25 Digital-to-Analog Converter 0 Registers Address Map (DAC1_BASE = $00 F1D0)
Register Acronym DAC1_CTRL DAC1_DATA DAC1_STEP DAC1_MINVAL DAC1_MAXVAL Address Offset $0 $1 $2 $3 $4 Control Register Data Register Step Register Minimum Value Register Maximum Value Register Register Description
Table 4-26 Comparator A Registers Address Map (CMPA_BASE = $00 F1E0)
Register Acronym CMPA_CTRL CMPA_STAT CMPA_FILT Address Offset $0 $1 $2 Control Register Status Register Filter Register Register Description
Table 4-27 Comparator B Registers Address Map (CMPB_BASE = $00 F1F0)
Register Acronym CMPB_CTRL CMPB_STAT Address Offset $0 $1 Control Register Status Register Register Description
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 53
Table 4-27 Comparator B Registers Address Map (Continued) (CMPB_BASE = $00 F1F0)
Register Acronym CMPB_FILT Address Offset $2 Filter Register Register Description
Table 4-28 Queued Serial Communication Interface 0 Registers Address Map (QSCI0_BASE = $00 F200)
Register Acronym QSCI0_RATE QSCI0_CTRL1 QSCI0_CTRL2 QSCI0_STAT QSCI0_DATA Address Offset $0 $1 $2 $3 $4 Register Description Baud Rate Register Control Register 1 Control Register 2 Status Register Data Register
Table 4-29 Queued Serial Peripheral Interface 0 Registers Address Map (QSPI0_BASE = $00 F220)
Register Acronym QSPI0_SCTRL QSPI0_DSCTRL QSPI0_DRCV QSPI0_DXMIT QSPI0_FIFO QSPI0_DELAY Address Offset $0 $1 $2 $3 $4 $5 Register Description Status and Control Register Data Size and Control Register Data Receive Register Data Transmit Register FIFO Control Register Delay Register
Table 4-30 I2C Registers Address Map (I2C_BASE = $00 F280)
Register Acronym I2C_CTRL I2C_TAR I2C_SAR I2C_DATA I2C_SSHCNT I2C_SSLCNT I2C_FSHCNT I2C_FSLCNT I2C_ISTAT I2C_IMASK Address Offset $0 $2 $4 $8 $A $C $E $10 $16 $18 Control Register Target Address Register Slave Address Register RX/TX Data Buffer and Command Register Standard Speed Clock SCL High Count Register Standard Speed Clock SCL Low Count Register Fast Speed Clock SCL High Count Register Fast Speed Clock SCL Low Count Register Interrupt Status Register Interrupt Mask Register Register Description
56F8035/56F8025 Data Sheet, Rev. 6 54 Freescale Semiconductor
Peripheral Memory-Mapped Registers
Table 4-30 I2C Registers Address Map (Continued) (I2C_BASE = $00 F280)
Register Acronym I2C_RISTAT I2C_RXFT I2C_TXFT I2C_CLRINT I2C_CLRRXUND I2C_CLRRXOVR I2C_CLRTXOVR I2C_CLRRDREQ I2C_CLRTXABRT I2C_CLRRXDONE I2C_CLRACT I2C_CLRSTPDET I2C_CLRSTDET I2C_CLRGC I2C_ENBL I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TXABRTSRC Address Offset $1A $1C $1E $20 $22 $24 $26 $28 $2A $2C $2E $30 $32 $34 $36 $38 $3A $3C $40 Register Description Raw Interrupt Status Register Receive FIFO Threshold Register Transmit FIFO Threshold Register Clear Combined and Individual Interrupts Register Clear RX_UNDER Interrupt Register Clear RX_OVER Interrupt Register Clear TX_OVER Interrupt Register Clear RD_REQ Interrupt Register Clear TX_ABRT Interrupt Register Clear RX_DONE Interrupt Register Clear Activity Interrupt Register Clear STOP_DET Interrupt Register Clear START_DET Interrupt Register Clear GEN_CALL Interrupt Register Enable Register Status Register Transmit FIFO Level Register Receive FIFO Level Register Transmit Abort Status Register
Table 4-31 Flash Module Registers Address Map (FM_BASE = $00 F400)
Register Acronym FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO FM_PROT FM_USTAT FM_CMD FM_DATA Address Offset $0 $1 $2 $3 $4 $5 - $9 $10 $11 - $12 $13 $14 $15 - $17 $18 $19 - $A Register Description Clock Divider Register Configuration Register Reserved Security High Half Register Security Low Half Register Reserved Protection Register Reserved User Status Register Command Register Reserved Data Buffer Register Reserved
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 55
Table 4-31 Flash Module Registers Address Map (FM_BASE = $00 F400) (Continued)
Register Acronym FM_IFROPT_1 FM_TSTSIG Address Offset $1B $1C $1D Register Description Information Option Register 1 Reserved Test Array Signature Register
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), to signals the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
* * * * Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Ability to drive initial address on the address bus after reset
For further information, see Table 4-2, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority and number 63 is the lowest.
5.3.1
Normal Interrupt Handling
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0
56F8035/56F8025 Data Sheet, Rev. 6 56 Freescale Semiconductor
Functional Description
and I1 bits in its status register.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 57
Table 5-1 Interrupt Mask Bit Definition
SR[9] (I1)
0 0 1 1
SR[8] (I0)
0 1 0 1
Exceptions Permitted Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3
Exceptions Masked None Priority 0 Priorities 0, 1 Priorities 0, 1, 2
The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E core.
Table 5-2 Interrupt Priority Encoding
IPIC_VALUE[1:0] 00 01 10 11 Current Interrupt Priority Level No interrupt or SWILP Priority 0 Priority 1 Priority 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts its Fast Interrupt handling.
56F8035/56F8025 Data Sheet, Rev. 6 58 Freescale Semiconductor
Block Diagram
5.4 Block Diagram
any0 Priority Level Level 0 64 -> 6 Priority Encoder
6
INT1
2 -> 4 Decode
INT VAB CONTROL IPIC
any3 Level 3 Priority Level 64 -> 6 Priority Encoder
IACK SR[9:8]
6
PIC_EN
INT64
2 -> 4 Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
* * Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 59
Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F0E0)
Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Vector Base Address Register Fast Interrupt Match 0 Register Fast Interrupt 0 Vector Address Low Register Fast Interrupt 0 Vector Address High 0 Register Fast Interrupt Match 1 Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 Reserved ICTRL $16 Interrupt Control Register Reserved 5.6.19 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18
56F8035/56F8025 Data Sheet, Rev. 6 60 Freescale Semiconductor
Register Descriptions
Add. Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11
Register Name IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
15
14
13
12
11 0 0 0 0
10 0 0 0 0
9
8
7
6
5
4
3
2
1
0
PLL IPL GPIOD IPL QSCI0_XMIT IPL I2C_ERR IPL TMRA_3 IPL PIT1 IPL 0 0 0 0 0 0
LVI IPL 0 0 0 0 0 0
RX_REG IPL 0 0
TX_REG IPL 0 0
TRBUF IPL FM_CBE IPL GPIOA IPL QSCI0_RCV IPL I2C_TX IPL TMRB_2 IPL ADCB_CC IPL
BKPT_U IPL FM_CC IPL GPIOB IPL QSCI0_RERR IPL I2C_RX IPL TMRB_1 IPL ADCA_CC IPL
STPCNT IPL FM_ERR IPL GPIOC IPL QSCI0_TIDL IPL I2C_GEN IPL TMRB_0 IPL PIT2 IPL
QSPI0_XMIT IPL 0 0
QSPI0_RCV IPL 0 0
TMRA_2 IPL PIT0 IPL 0 0
TMRA_1 IPL COMPB IPL PWM_F IPL
TMRA_0 IPL COMPA IPL PWM_RL IPL
I2C_STAT IPL TMRB_3 IPL ADC_ZC IPL
VECTOR_BASE_ADDRESS 0 0 0 0 0 0 0 0 FAST INTERRUPT 0
FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT 1
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 1
PENDING[16:2] PENDING[32:17] PENDING[48:33] PENDING[63:49]
$16
ICTRL Reserved
INT
IPIC
VAB
INT_ DIS
1
1
1
0
0
= Reserved
Figure 5-2 ITCN Register Map Summary
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 61
5.6.1
Interrupt Priority Register 0 (IPR0)
15 14 13 12 11
0
Base + $0 Read Write RESET
10
0
9
8
7
6
5
4
3
2
1
0
PLL IPL 0 0 0
LVI IPL 0
RX_REG IPL 0 0
TX_REG IPL 0 0
TRBUF IPL 0 0
BKPT_U IPL 0 0
STPCNT IPL 0 0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)--Bits 15-14
This field is used to set the interrupt priority levels for the PLL Loss of Reference or Change in Lock Status IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.2
Low Voltage Detector Interrupt Priority Level (LVI IPL)--Bits 13-12
This field is used to set the interrupt priority levels for the Low Voltage Detector IRQ. This IRQ is limited to priorities 1 through 3 and is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.3 5.6.1.4
Reserved--Bits 11-10 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)-- Bits 9-8
This bit field is reserved. Each bit must be set to 0.
This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
56F8035/56F8025 Data Sheet, Rev. 6 62 Freescale Semiconductor
Register Descriptions
5.6.1.5
EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)-- Bits 7-6
This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.6
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)-- Bits 5-4
This field is used to set the interrupt priority level for the EOnCE Trace Buffer IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.7
EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)-- Bits 3-2
This field is used to set the interrupt priority level for the EOnCE Breakpoint Unit IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.8
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)-- Bits 1-0
This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 63
5.6.2
Interrupt Priority Register 1 (IPR1)
15 14 13
0
Base + $1 Read Write RESET
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
GPIOD IPL 0 0
FM_CBE IPL 0 0
FM_CC IPL 0 0
FM_ERR IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
GPIOD Interrupt Priority Level (GPIOD IPL)--Bits 15-14
This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.2.2 5.6.2.3
Reserved--Bits 13-6 FM Command, Data, Address Buffers Empty Interrupt Priority Level (FM_CBE IPL)--Bits 5-4
This bit field is reserved. Each bit must be set to 0.
This field is used to set the interrupt priority level for the FM Command, Data Address Buffers Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.2.4
FM Command Complete Interrupt Priority Level (FM_CC IPL)--Bits 3-2
This field is used to set the interrupt priority level for the FM Command Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 64 Freescale Semiconductor
Register Descriptions
5.6.2.5
FM Error Interrupt Priority Level (FM_ERR IPL)--Bits 1-0
This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3
Interrupt Priority Register 2 (IPR2)
15 14 13
0
Base + $2 Read Write RESET
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
QSCI0_XMIT IPL 0 0
QSPI0_XMIT IPL 0 0
QSPI0_RCV IPL 0 0
GPIOA IPL 0 0
GPIOB IPL 0 0
GPIOC IPL 0 0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)-- Bits 15-14
This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.2 5.6.3.3
Reserved--Bits 13-10 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)-- Bits 9-8
This bit field is reserved. Each bit must be set to 0.
This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 65
5.6.3.4
QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)--Bits 7-6
This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.5
GPIOA Interrupt Priority Level (GPIOA IPL)--Bits 5-4
This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.6
GPIOB Interrupt Priority Level (GPIOB IPL)--Bits 3-2
This field is used to set the interrupt priority level for the GPIOB IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.7
GPIOC Interrupt Priority Level (GPIOC IPL)--Bits 1-0
This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3 Read Write RESET 15 14 13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
I2C_ERR IPL 0 0
QSCI0_RCV IPL 0 0
QSCI0_RERR IPL 0 0
QSCI0_TIDL IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-6 Interrupt Priority Register 3 (IPR3)
56F8035/56F8025 Data Sheet, Rev. 6 66 Freescale Semiconductor
Register Descriptions
5.6.4.1
I2C Error Interrupt Priority Level (I2C_ERR IPL)--Bits 15-14
This field is used to set the interrupt priority level for the I2C Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.2 5.6.4.3
Reserved--Bits 13-6 QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)--Bits 5-4
This bit field is reserved. Each bit must be set to 0.
This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.4
QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)-- Bits 3-2
This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.5
QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)-- Bits 1-0
This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 67
5.6.5
Interrupt Priority Register 4 (IPR4)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write RESET
Base + $4
TMRA_3 IPL 0 0
TMRA_2 IPL 0 0
TMRA_1 IPL 0 0
TMRA_0 IPL 0 0
I2C_STAT IPL 0 0
I2C_TX IPL 0 0
I2C_RX IPL 0 0
I2C_GEN IPL 0 0
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1
Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.2
Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)-- Bits 13-12
This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.3
Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)-- Bits 11-10
This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 68 Freescale Semiconductor
Register Descriptions
5.6.5.4
Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)-- Bits 9-8
This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.5
I2C Status Interrupt Priority Level (I2C_STAT IPL)--Bits 7-6
This field is used to set the interrupt priority level for the I2C Status IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.6
I2C Transmit Interrupt Priority Level (I2C_TX IPL)--Bits 5-4
This field is used to set the interrupt priority level for the I2C Transmit IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.7
I2C Receive Interrupt Priority Level (I2C_RX IPL)-- Bits 3-2
This field is used to set the interrupt priority level for the I2C Receiver IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.8
I2C General Call Interrupt Priority Level (I2C_GEN IPL)--Bits 1-0
This field is used to set the interrupt priority level for the I2C General Call IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * 00 = IRQ disabled (default) 01 = IRQ is priority level 0
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 69
* *
10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6
Interrupt Priority Register 5 (IPR5)
15 14 13 12 11 10 9 8 7
0
Base + $5 Read Write RESET
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PIT1 IPL 0 0
PIT0 IPL 0 0
COMPB IPL 0 0
COMPA IPL 0 0
0
0
0
0
0
0
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR6)
5.6.6.1
Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.2
Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)-- Bits 13-12
This field is used to set the interrupt priority level for the Programmable Interval Timer 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.3
Comparator B Interrupt Priority Level (COMPB IPL)-- Bits 11-10
This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 70 Freescale Semiconductor
Register Descriptions
5.6.6.4
Comparator A Interrupt Priority Level (COMPA IPL)-- Bits 9-8
This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.5
Reserved--Bits 7-0
This bit field is reserved. Each bit must be set to 0.
5.6.7
Interrupt Priority Register 6 (IPR6)
15
0
Base + $6 Read Write RESET
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
PWM_F IPL 0 0
PWM_RL IPL 0 0
ADC_ZC IPL 0 0
ADCB_CC IPL 0 0
ADCA_CC IPL 0 0
PIT2 IPL 0 0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1 5.6.7.2
Reserved--Bits 15-12 PWM Fault Interrupt Priority Level (PWM_F IPL)--Bits 11-10
This bit field is reserved. Each bit must be set to 0.
This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.3
Reload PWM Interrupt Priority Level (PWM_RL IPL)--Bits 9-8
This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 71
5.6.7.4
ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)--Bits 7-6
This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.5
ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)--Bits 5-4
This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.6
ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)--Bits 3-2
This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.7
Programmable Interval Timer 2 Interrupt Priority Level (PIT2 IPL)--Bits 1-0
This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
* * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
56F8035/56F8025 Data Sheet, Rev. 6 72 Freescale Semiconductor
Register Descriptions
5.6.8
Vector Base Address Register (VBA)
15
0
Base + $7 Read Write RESET1
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VECTOR_BASE_ADDRESS 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0
0
1. The 56F8035 resets to a value of 0 x 0000. This corresponds to reset addresses of 0 x 000000. The 56F8025 resets to a value of 0 x 0080. This corresponds to reset addresses of 0 x 004000.
Figure 5-10 Vector Base Address Register (VBA)
5.6.8.1 5.6.8.2
Reserved--Bits 15-14 Vector Address Bus (VAB) Bits 13-0
This bit field is reserved. Each bit must be set to 0.
The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core.
5.6.9
Fast Interrupt Match 0 Register (FIM0)
15
0
Base + $8 Read Write RESET
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
FAST INTERRUPT 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
Figure 5-11 Fast Interrupt Match 0 Register (FIM0)
5.6.9.1 5.6.9.2
Reserved--Bits 15-6 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)--Bits 5-0
This bit field is reserved. Each bit must be set to 0.
These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 73
5.6.10
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write
Base + $9
FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESET
Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.10.1
Fast Interrupt 0 Vector Address Low (FIVAL0)--Bits 15-0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.11
Fast Interrupt 0 Vector Address High Register (FIVAH0)
15
0
Base + $A Read Write RESET
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.11.1 5.6.11.2
Reserved--Bits 15-5 Fast Interrupt 0 Vector Address High (FIVAH0)--Bits 4-0
This bit field is reserved. Each bit must be set to 0.
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.12
Fast Interrupt 1 Match Register (FIM1)
15
0
Base + $B Read Write RESET
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
FAST INTERRUPT 1 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 1 Match Register (FIM1)
5.6.12.1 5.6.12.2
Reserved--Bits 15-6 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)--Bits 5-0
This bit field is reserved. Each bit must be set to 0.
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
56F8035/56F8025 Data Sheet, Rev. 6 74 Freescale Semiconductor
Register Descriptions
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table.
5.6.13
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write
Base + $C
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESET
Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.13.1
Fast Interrupt 1 Vector Address Low (FIVAL1)--Bits 15-0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.14
Fast Interrupt 1 Vector Address High (FIVAH1)
15
0
Base + $D Read Write RESET
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.14.1 5.6.14.2
Reserved--Bits 15-5 Fast Interrupt 1 Vector Address High (FIVAH1)--Bits 4-0
This bit field is reserved. Each bit must be set to 0.
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.15
IRQ Pending Register 0 (IRQP0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
Base + $E Read Write RESET
PENDING[16:2]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-17 IRQ Pending Register 0 (IRQP0)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 75
5.6.15.1
IRQ Pending (PENDING)--Bits 16-2
These register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations.
* * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.15.2
Reserved--Bit 0
This bit field is reserved. It must be set to 1.
5.6.16
IRQ Pending Register 1 (IRQP1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write
PENDING[32:17]
Base + $F
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-18 IRQ Pending Register 1 (IRQP1)
5.6.16.1
IRQ Pending (PENDING)--Bits 32-17
These register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations.
* * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.17
IRQ Pending Register 2 (IRQP2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write
PENDING[48:33]
Base + $10
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-19 IRQ Pending Register 2 (IRQP2)
5.6.17.1
IRQ Pending (PENDING)--Bits 48-33
These register bit values represent the pending IRQs for interrupt vector numbers 33 through 48. Ascending IRQ numbers correspond to ascending bit locations.
* * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
56F8035/56F8025 Data Sheet, Rev. 6 76 Freescale Semiconductor
Register Descriptions
5.6.18
IRQ Pending Register 3 (IRQP3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write
PENDING[63:49]
Base + $11
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-20 IRQ Pending Register 3 (IRQP3)
5.6.18.1
IRQ Pending (PENDING)--Bits 63-49
These register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending IRQ numbers correspond to ascending bit locations.
* * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.19
Interrupt Control Register (ICTRL)
15
INT
$Base + $16 Read Write RESET
14
IPIC
13
12
11
10
9
VAB
8
7
6
5
INT_ DIS
4
1
3
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
Figure 5-21 Interrupt Control Register (ICTRL)
5.6.19.1
* *
Interrupt (INT)--Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core
5.6.19.2
Interrupt Priority Level (IPIC)--Bits 14-13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service routine.
Note: * * * * Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 77
Table 5-4 Interrupt Priority Encoding
IPIC_VALUE[1:0] 00 01 10 11 Current Interrupt Priority Level No interrupt or SWILP Priority 0 Priority 1 Priority 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3
5.6.19.3
Vector Number - Vector Address Bus (VAB)--Bits 12-6
This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken. In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when the 56800E core jumps to a new interrupt service routine.
Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it.
5.6.19.4
* *
Interrupt Disable (INT_DIS)--Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default) 1 = All interrupts disabled
5.6.19.5 5.6.19.6
Reserved--Bits 4-2 Reserved--Bits 1-0
This bit field is reserved. Each bit must be set to 1.
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1 General
Table 5-5 Reset Summary
Reset
Core Reset
Priority
Source RST
Characteristics Core reset from the SIM
56F8035/56F8025 Data Sheet, Rev. 6 78 Freescale Semiconductor
Introduction
5.7.2
5.7.2.1
Description of Reset Operation
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-22.
RES CLK VAB PAB RESET_VECTOR_ADR READ_ADR
Figure 5-22 Reset Interface
5.7.3
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities:
* * * * * * * * Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module's functions are discussed in more detail in the following sections.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 79
6.2 Features
The SIM has the following features:
* * * * * * * * * Chip reset sequencing Core and peripheral clock control and distribution Stop/Wait mode control System status control Registers containing the JTAG ID of the chip Controls for programmable peripheral and GPIO connections Peripheral clocks for TMR and PWM with a high-speed (3X) option Power-saving clock gating for peripherals Three power modes (Run, Wait, Stop) to control power utilization -- Stop mode shuts down the 56800E core, system clock, and peripheral clock -- Wait mode shuts down the 56800E core and unnecessary system clock operation -- Run mode supports full device operation Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection capability Controls the enable/disable functions of Large Regulator Standby mode with write protection capability Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts Controls for programmable peripheral and GPIO connections Software chip reset I/O short address base location control Peripheral protection control to provide runaway code protection for safety-critical applications Controls output of internal clock sources to CLKO pin Four general-purpose software control registers are reset only at power-on Peripherals Stop mode clocking control
* * * * * * * * * *
56F8035/56F8025 Data Sheet, Rev. 6 80 Freescale Semiconductor
Register Descriptions
6.3 Register Descriptions
A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data.
Table 6-1 SIM Registers (SIM_BASE = $00 F100)
Register Acronym CTRL RSTAT SWC0 SWC1 SWC2 SWC3 MSHID LSHID PWR Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Power Control Register Reserved CLKOUT PCR PCE0 PCE1 SD0 SD1 IOSAHI IOSALO PROT GPSA0 GPSA1 GPSB0 GPSB1 GPSCD IPS0 IPS1 IPS2 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A CLKO Select Register Peripheral Clock Rate Register Peripheral Clock Enable Register 0 Peripheral Clock Enable Register 0 Stop Disable Register 0 Stop Disable Register 1 I/O Short Address Location High Register I/O Short Address Location Low Register Protection Register GPIO Peripheral Select Register 0 for GPIOA GPIO Peripheral Select Register 1 for GPIOA GPIO Peripheral Select Register 0 for GPIOB GPIO Peripheral Select Register 1 for GPIOB GPIO Peripheral Select Register for GPIOC and GPIOD Internal Peripheral Source Select Register 0 for PWM Internal Peripheral Source Select Register 1 for DACs Internal Peripheral Source Select Register 2 for Quad Timer A Reserved 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 6.3.20 6.3.21 6.3.22 6.3.23 Register Name Section Location 6.3.1 6.3.2 6.3.3 6.3.3 6.3.3 6.3.3 6.3.4 6.3.5 6.3.6
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 81
Add. Offset $0
Address Acronym SIM_ CTRL SIM_ RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ONCE EBL0
4
SW RST
3
2
1
0
STOP_ DISABLE POR
WAIT_ DISABLE 0 0
$1
0
0
0
0
0
0
0
0
0
SWR
COP_ COP_ EXTR TOR LOR
$2 $3 $4 $5 $6 $7 $8
Software Control Data 0 Software Control Data 1 Software Control Data 2 Software Control Data 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1
LRSTDBY
$A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A
SIM_ CLKOUT SIM_PCR SIM_PCE0 SIM_PCE1 SIM_SD0 SIM_SD1 SIM_IOSAHI SIM_IOSALO SIM_PROT SIM_GPSA0 SIM_GPSA1 SIM_GPSB0 SIM_GPSB1 SIM_GPSCD SIM_IPS0 SIM_IPS1 SIM_IPS2
0 0
0
0
0
0 0 0 0 0 0 0
0 0
PWM3 PWM2 PWM1 PWM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0
0 0
0 0 0
0 0
0 0 0
0 0
TMRA_ CR CMPA PIT2
PWM_ CR DAC1 PIT1 DAC1_ SD PIT1_SD 0
I2C_ CR DAC0 PIT0 DAC0_ SD PIT0_ SD 0
CMPB 0
ADC 0
I2C 0
QSCI0 0
QSPI0 TA2 QSPI0 _SD TA2_ SD 0
PWM TA0 PWM_ SD TA0_ SD
TA3 0
TA1 0
CMPB_ CMPA_ SD SD 0 0 PIT2_ SD 0
ADC_ SD 0 0
I2C_ SD 0 0
QSCI0 _SD 0 0
TA3_ SD 0
TA1_ SD
ISAL[23:22]
ISAL[21:6] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCEP 0 0 GIPSP 0
GPS_ A6 0
GPS_A5 0 0 0 0 0 0 0 0
GPS_A4 0 0 0 0 0 0 0 0 0
GPS_ A11
GPS_ A10
GPS_A9 0 0 0 GPS_ B1 0 0
GPS_A8 0 0 0 GPS_ B0 GPS_ B7 0
GPS_B6 0 0
GPS_B5 0 0 0
GPS_B3 0 0 GPS_ B10 0
GPS_B2 0 0 0 0
GPS_ B11 0 0 0
GPS_ D5 0 0
IPS0_ FAULT2 0 0
IPS0_ FAULT1 0 0
IPS0_PSRC1 0 0 0 IPS1_DSYNC1 0 IPS2_ TA1 0 0
IPS0_PSRC0 IPS1_DSYNC0 0 0 0
IPS2_ TA3
IPS2_ TA2
56F8035/56F8025 Data Sheet, Rev. 6 82 Freescale Semiconductor
Register Descriptions
Reserved
0 = Read as 0 1
= Read as 1
= Reserved
Figure 6-1 SIM Register Map Summary
6.3.1
SIM Control Register (SIM_CTRL)
15
0
Base + $0 Read Write RESET
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ONCE EBL 0
4
SW RST 0
3
2
1
0
STOP_ DISABLE 0 0
WAIT_ DISABLE 0 0
0
0
0
0
0
0
0
0
0
0
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1 6.3.1.2
* * Note:
Reserved--Bits 15-6 OnCE Enable (ONCEEBL)--Bit 5
This bit field is reserved. Each bit must be set to 0.
0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled Using default state "0" is recommended.
6.3.1.3
* *
Software Reset (SWRST)--Bit 4
Writing 1 to this field will cause the device to reset Read is zero
6.3.1.4
* * * *
Stop Disable (STOP_DISABLE)--Bits 3-2
00 = Stop mode will be entered when the 56800E core executes a STOP instruction 01 = The 56800E STOP instruction will not cause entry into Stop mode 10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the STOP_DISABLE field is write-protected until the next reset 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is write-protected until the next reset
6.3.1.5
* * * *
Wait Disable (WAIT_DISABLE)--Bits 1-0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction 01 = The 56800E WAIT instruction will not cause entry into Wait mode 10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 83
6.3.2
SIM Reset Status Register (SIM_RSTAT)
This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On Reset has deasserted.
Base + $1 Read Write RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
COP_ LOR
3
EXTR
2
POR
1
0
0
0
COP_ SWR TOR
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
6.3.2.1 6.3.2.2
Reserved--Bits 15-7 Software Reset (SWR)--Bit 6
This bit field is reserved. Each bit must be set to 0.
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written 1 to SWRST bit in the SIM_CTRL register).
6.3.2.3
COP Time-Out Reset (COP_TOR)--Bit 5
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.4
COP Loss of Reference Reset (COP_LOR)--Bit 4
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.5 6.3.2.6
External Reset (EXTR)--Bit 3 Power-On Reset (POR)--Bit 2
When set, this bit indicates that the previous system reset was caused by an external reset.
This bit is set during a Power-On Reset.
56F8035/56F8025 Data Sheet, Rev. 6 84 Freescale Semiconductor
Register Descriptions
6.3.2.7
Reserved--Bits 1-0
This bit field is reserved. Each bit must be set to 0.
6.3.3
SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3)
These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow.
Base + $2 Read Write RESET
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Software Control Data 0 - 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)
6.3.3.1
Software Control Register 0 - 3 (FIELD)--Bits 15-0
This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to contain data that will be unaffected by the other reset sources (external reset, software reset, and COP reset).
6.3.4
Most Significant Half of JTAG ID (SIM_MSHID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2.
Base + $6 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
1
4
1
3
0
2
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
6.3.5
Least Significant Half of JTAG ID (SIM_LSHID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $801D.
Base + $7 Read Write RESET
15
1
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 85
6.3.6
SIM Power Control Register (SIM_PWR)
This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption. Refer to the overview of power-down modes and the overview of clock generation for more information on the use of large regulator standby.
Base + $8 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LRSTDBY 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-7 SIM Power Control Register (SIM_PWR)
6.3.6.1 6.3.6.2
* * * *
Reserved--Bits 15-2 Large Regulator Standby Mode (LRSTDBY)--Bits 1-0
This bit field is reserved. Each bit must be set to 0.
00 = Large regulator is in Normal mode 01 = Large regulator is in Standby (reduced-power) mode 10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset 11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
6.3.7
Clock Output Select Register (SIM_CLKOUT)
The Clock Output Select register can be used to multiplex out selected clock sources generated inside the clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source to the output is unspecified. The observability of the clock output signals at output pads is subject to the frequency limitations of the associated IO cell. GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for the peripheral function of GPIOA[3:0] to be programmed as PWM (selected by bits [9:6] of the Clock Output Select register). See Figure 6-8 for details.
Base + $A Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
PWM3 0
8
PWM2 0
7
6
5
1
4
0
3
0
2
0
1
0
0
0
PWM1 PWM0 0 0
0
0
0
0
0
0
1
0
0
0
0
0
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
56F8035/56F8025 Data Sheet, Rev. 6 86 Freescale Semiconductor
Register Descriptions
6.3.7.1 6.3.7.2
* *
Reserved--Bits 15-10 PWM3--Bit 9
This bit field is reserved. Each bit must be set to 0.
0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
* *
PWM2--Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2 1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
* *
PWM1--Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1 1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
6.3.7.5
* *
PWM0--Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0 1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
6.3.7.6 6.3.7.7
Reserved--Bit 5 Reserved--Bits 4-0
This bit field is reserved for factory test. It must be set to 1.
This bit field is reserved for factory test. Each bit must be set to 0.
6.3.8
Peripheral Clock Rate Register (SIM_PCR)
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it.
Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured.
Base + $B Read Write RESET
15
0
14
13
12
I2C_ CR 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
TMRA_ PWM_ CR CR 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
6.3.8.1
Reserved--Bits 15
This bit field is reserved. Each bit must be set to 0.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 87
6.3.8.2
* *
Quad Timer A Clock Rate (TMRA_CR)--Bit 14
This bit selects the clock speed for the Quad Timer A module.
0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.3
* *
Pulse Width Modulator Clock Rate (PWM_CR)--Bit 13
This bit selects the clock speed for the PWM module.
0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.4
* *
Inter-Integrated Circuit Run Clock Rate (I2C_CR)--Bit 12
This bit selects the clock speed for the I2C run clock.
0 = I2C module run clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = I2C module run clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.5
Reserved--Bits 11-0
This bit field is reserved. Each bit must be set to 0.
6.3.9
Peripheral Clock Enable Register 0 (SIM_PCE0)
The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use. When a peripheral's clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock is shut off. IPBus writes are not possible. Setting the PCE bit does not guarantee that the peripheral's clock is running. Enabled peripheral clocks will still become disabled in Stop mode, unless the peripheral's Stop Disable control in the SDn register is set to 1.
Base + $C Read Write RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15
CMPB
14
CMPA
13
DAC1
12
DAC0
11
0
10
ADC
9
0
8
0
7
0
6
I2C
5
0
4
QSCI0
3
0
2
QSPI0
1
0
0
PWM
Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)
6.3.9.1
* *
Comparator B Clock Enable (CMPB)--Bit 15
0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled) 1 = The clock is enabled to the Comparator B module
6.3.9.2
* *
Comparator A Clock Enable (CMPA)--Bit 14
0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled) 1 = The clock is enabled to the Comparator A module
56F8035/56F8025 Data Sheet, Rev. 6
88
Freescale Semiconductor
Register Descriptions
6.3.9.3
* *
Digital-to-Analog Clock Enable 1 (DAC1)--Bit 13
0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled) 1 = The clock is enabled to the DAC1 module
6.3.9.4
* *
Digital-to-Analog Clock Enable 0 (DAC0)--Bit 12
0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled) 1 = The clock is enabled to the DAC0 module
6.3.9.5 6.3.9.6
* *
Reserved--Bit 11 Analog-to-Digital Converter Clock Enable (ADC)--Bit 10
This bit field is reserved. It must be set to 0.
0 = The clock is not provided to the ADC module (the ADC module is disabled) 1 = The clock is enabled to the ADC module
6.3.9.7 6.3.9.8
* *
Reserved--Bits 9-7 Inter-Integrated Circuit IPBus Clock Enable (I2C)--Bit 6
This bit field is reserved. Each bit must be set to 0.
0 = The clock is not provided to the I2C module (the I2C module is disabled) 1 = The clock is enabled to the I2C module
6.3.9.9 6.3.9.10
* *
Reserved--Bit 5 QSCI 0 Clock Enable (QSCI0)--Bit 4
This bit field is reserved. It must be set to 0.
0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled) 1 = The clock is enabled to the QSCI0 module
6.3.9.11 6.3.9.12
* *
Reserved--Bit 3 QSPI 0 Clock Enable (QSPI0)--Bit 2
This bit field is reserved. It must be set to 0.
0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled) 1 = The clock is enabled to the QSPI0 module
6.3.9.13 6.3.9.14
*
Reserved--Bit 1 PWM Clock Enable (PWM)--Bit 0
This bit field is reserved. It must be set to 0.
0 = The clock is not provided to the PWM module (the PWM module is disabled)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 89
*
1 = The clock is enabled to the PWM module
6.3.10
Peripheral Clock Enable Register 1 (SIM_PCE1)
See Section 6.3.9 for general information about Peripheral Clock Enable registers.
Base + $D Read Write RESET
15
0
14
PIT2
13
PIT1 0
12
PIT0 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
TA3
2
TA2 0
1
TA1 0
0
TA0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
6.3.10.1 6.3.10.2
* *
Reserved--Bit 15 Programmable Interval Timer 2 Clock Enable (PIT2)--Bit 14
This bit field is reserved. It must be set to 0.
0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled) 1 = The clock is enabled to the PIT2 module
6.3.10.3
* *
Programmable Interval Timer 1 Clock Enable (PIT1)--Bit 13
0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled) 1 = The clock is enabled to the PIT1 module
6.3.10.4
* *
Programmable Interval Timer 0 Clock Enable (PIT0)--Bit 12
0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled) 1 = The clock is enabled to the PIT0 module
6.3.10.5 6.3.10.6
* *
Reserved--Bits 11-4 Quad Timer A, Channel 3 Clock Enable (TA3)--Bit 3
This bit field is reserved. Each bit must be set to 0.
0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled) 1 = The clock is enabled to the Timer A3 module
6.3.10.7
* *
Quad Timer A, Channel 2 Clock Enable (TA2)--Bit 2
0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled) 1 = The clock is enabled to the Timer A2 module
6.3.10.8
* *
Quad Timer A, Channel 1 Clock Enable (TA1)--Bit 1
0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled) 1 = The clock is enabled to the Timer A1 module
56F8035/56F8025 Data Sheet, Rev. 6 90 Freescale Semiconductor
Register Descriptions
6.3.10.9
* *
Quad Timer A, Channel 0 Clock Enable (TA0)--Bit 0
0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) 1 = The clock is enabled to the Timer A0 module
6.3.11
Stop Disable Register 0 (SD0)
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the system to return to Run mode, this feature is provided so that selected peripherals can be left operating in Stop mode for the purpose of generating a wake-up interrupt. For power-conscious applications, it is recommended that only a minimum set of peripherals be configured to remain operational during Stop mode. Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless their corresponding Stop Disable control is set to 1. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. Reads and writes cannot be made to a module that has its clock disabled.
Base + $E Read Write RESET
15
14
13
12
11
0
10
ADC_ SD 0
9
0
8
0
7
0
6
I2C_ SD 0
5
0
4
QSCI0_ SD 0
3
0
2
QSPI0_ SD 0
1
0
0
PWM_ SD 0
CMPB_ CMPA_ DAC1_ DAC0_ SD SD SD SD 0 0 0 0
0
0
0
0
0
0
0
Figure 6-12 Stop Disable Register 0 (SD0)
6.3.11.1
* *
Comparator B Clock Stop Disable (CMPB_SD)--Bit 15
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.2
* *
Comparator A Clock Stop Disable (CMPA_SD)--Bit 14
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.3
* *
Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)--Bit 13
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.4
*
Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)--Bit 12
0 = The clock is disabled during Stop mode
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 91
*
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.5 6.3.11.6
* *
Reserved--Bit 11 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)--Bit 10
This bit field is reserved. It must be set to 0.
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.7 6.3.11.8
* *
Reserved--Bits 9-7 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)--Bit 6
This bit field is reserved. Each bit must be set to 0.
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.9
Reserved--Bit 5
This bit field is reserved. It must be set to 0.
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)--Bit 4
* * 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.11 Reserved--Bit 3
This bit field is reserved. It must be set to 0.
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)--Bit 2
Each bit controls clocks to the indicated peripheral.
* * 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
6.3.11.13 Reserved--Bit 1
This bit field is reserved. It must be set to 0.
6.3.11.14 PWM Clock Stop Disable (PWM_SD)--Bit 0
* * 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register
56F8035/56F8025 Data Sheet, Rev. 6 92 Freescale Semiconductor
Register Descriptions
6.3.12
Stop Disable Register 1 (SD1)
See Section 6.3.11 for general information about Stop Disable Registers.
Base + $F Read Write RESET
15
0
14
PIT2_ SD 0
13
PIT1_ SD 0
12
PIT0_ SD 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
TA3_ SD 0
2
TA2_ SD 0
1
TA1_ SD 0
0
TA0_ SD 0
0
0
0
0
0
0
0
0
0
Figure 6-13 Stop Disable Register 1 (SD1)
6.3.12.1 6.3.12.2
* *
Reserved--Bit 15 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)--Bit 14
This bit field is reserved. It must be set to 0.
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.12.3
* *
Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)--Bit 13
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.12.4
* *
Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)--Bit 12
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.12.5 6.3.12.6
* *
Reserved--Bits 11-4 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)--Bit 3
This bit field is reserved. Each bit must be set to 0.
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.12.7
* *
Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)--Bit 2
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 93
6.3.12.8
* *
Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)--Bit 1
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.12.9
* *
Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)--Bit 0
0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register
6.3.13
I/O Short Address Location Register High (SIM_IOSAHI)
In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits are "hard coded" to a specific area of memory. This scheme allows efficient access to a 64-location area in peripheral space with single word instruction. Short address location registers specify the upper 18 bits of I/O address, which are "hard coded". These registers allow access to peripherals using I/O short address mode, regardless of the physical location of the peripheral, as shown in Figure 6-14. "Hard Coded" Address Portion
6 Bits from I/O Short Address Mode Instruction Instruction Portion
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
Figure 6-14 I/O Short Address Determination With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its peripheral registers and then use the I/O short addressing mode to access them.
Note: Note: The default value of this register set points to the EOnCE registers. The pipeline delay between setting this register set and using short I/O addressing with the new value is five instruction cycles.
56F8035/56F8025 Data Sheet, Rev. 6 94 Freescale Semiconductor
Register Descriptions
Base + $10 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ISAL[23:22] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)
6.3.13.1 6.3.13.2
Reserved--Bits 15--2 Input/Output Short Address Location (ISAL[23:22])--Bits 1-0
This bit field is reserved. Each bit must be set to 0.
This field represents the upper two address bits of the "hard coded" I/O short address.
6.3.14
I/O Short Address Location Register Low (SIM_IOSALO)
See Section 6.3.13 for general information about I/O short address location registers.
Base + $11 Read Write RESET
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISAL[21:6] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.14.1
Input/Output Short Address Location (ISAL[21:6])--Bits 15-0
This field represents the lower 16 address bits of the "hard coded" I/O short address.
6.3.15
Protection Register (SIM_PROT)
This register provides write protection of selected control fields for safety-critical applications. The primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP) field protects the SIM registers' contents, which contain peripheral clock controls. Some peripherals provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for details. Flexibility is provided so that write protection control values may themselves be optionally locked (write-protected). Protection controls in this register have two bit values which determine the setting of the control and whether the value is locked. While a protection control remains unlocked, protection can be disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by a chip reset, which restores its default non-locked value.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 95
Base + $12 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
PCEP 0
2
1
0
GIPSP 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-17 Protection Register (SIM_PROT)
6.3.15.1 6.3.15.2
* * * *
Reserved--Bits 15-4 Peripheral Clock Enable Protection (PCEP)--Bits 3-2
This bit field is reserved. Each bit must be set to 0.
These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
00 = Write protection off (default) 01 = Write protection on 10 = Write protection off and locked until chip reset 11 = Write protection on and locked until chip reset
6.3.15.3
GPIO and Internal Peripheral Select Protection (GIPSP)--Bits 1-0
These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.
* * * * Note: 00 = Write protection off (default) 01 = Write protection on 10 = Write protection off and locked until chip reset 11 = Write protection on and locked until chip reset The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for in-house test only.
6.3.16
SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn registers select which peripheral function has control of the I/O. Figure 6-18 illustrates the output path to an I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function inputs to receive input from the properly selected I/O pin.
56F8035/56F8025 Data Sheet, Rev. 6 96 Freescale Semiconductor
Register Descriptions
GPIOA6_PEREN Register SIM_GPSA0 Register GPIOA6
0 GPIOA6 pin 1
PWM FAULT0
0
Timer A0
1
Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one of these I/O must be configured to control that peripheral function. If more than one I/O is configured to control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input signal will be the logical OR and AND of all the I/O signals. Complete lists of I/O muxings are provided in Table 2-3. The GPSn setting can be altered during normal operation, but a delay must be inserted between the time when one function is disabled and another function is enabled.
Note: After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin.
Base + $13 Read Write RESET
15
0
14
0
13
0
12
GPS_A6 0
11
10
9
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
GPS_A5 0 0
GPS_A4 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
6.3.16.1 6.3.16.2
* *
Reserved--Bits 15-13 Configure GPIOA6 (GPS_A6)--Bit 12
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate function for GPIOA6.
0 = FAULT0 - PWM FAULT0 Input (default) 1 = TA0 - Timer A0
6.3.16.3
*
Configure GPIOA5 (GPS_A5)--Bits 11-10
This field selects the alternate function for GPIOA5.
00 = PWM5 - PWM5 (default)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 97
* * *
01 = FAULT2 - PWM FAULT2 Input 10 = TA3 - Timer A3 11 = Reserved
6.3.16.4
* * * *
Configure GPIOA4 (GPS_A4)--Bits 9-8
This field selects the alternate function for GPIOA4.
00 = PWM4 - PWM4 (default) 01 = FAULT1 - PWM FAULT1 Input 10 = TA2 - Timer A2 11 = Reserved
6.3.16.5
Reserved--Bits 7-0
This bit field is reserved. Each bit must be set to 0.
6.3.17
SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $14 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
GPS_ A11 0
5
0
4
GPS_ A10 0
3
2
1
0
GPS_A9 0 0
GPS_A8 0 0
0
0
0
0
0
0
0
0
0
0
Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
6.3.17.1 6.3.17.2
* *
Reserved--Bits 15-7 Configure GPIOA11 (GPS_A11)--Bit 6
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate function for GPIOA11.
0 = CINB - Comparator B Input 2 (default) 1 = Reserved
6.3.17.3 6.3.17.4
* *
Reserved--Bit 5 Configure GPIOA10 (GPS_A10)--Bit 4
This bit field is reserved. It must be set to 0.
This field selects the alternate function for GPIOA10.
0 = CINA- Comparator A Input 2 (default) 1 = Reserved
6.3.17.5
Configure GPIOA9 (GPS_A9)--Bits 3-2
This field selects the alternate function for GPIOA9.
56F8035/56F8025 Data Sheet, Rev. 6 98 Freescale Semiconductor
Register Descriptions
* * * *
00 = FAULT2 - PWM FAULT2 Input (default) 01 = TA3 - Timer A3 10 = CMPBI1 - Comparator B Input 1 11 = Reserved
6.3.17.6
* * * *
Configure GPIOA8 (GPS_A8)--Bits 1-0
This field selects the alternate function for GPIOA8.
00 = FAULT1 - PWM FAULT1 Input (default) 01 = TA2 - Timer A2 10 = CMPAI1 - Comparator A Input 1 11 = Reserved
6.3.18
SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $15 Read Write RESET
15
0
14
13
12
11
10
0
9
0
8
0
7
6
5
4
3
0
2
GPS_ B1 0
1
0
0
GPS_ B0 0
GPS_B6 0 0
GPS_B5 0 0
GPS_B3 0 0
GPS_B2 0 0
0
0
0
0
0
0
Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)
6.3.18.1 6.3.18.2
* * * *
Reserved--Bit 15 Configure GPIOB6 (GPS_B6)--Bits 14-13
This bit field is reserved. It must be set to 0.
This field selects the alternate function for GPIOB6.
00 = RXD0 - QSCI0 Receive Data (default) 01 = SDA - I2C Serial Data 10 = CLKIN - External Clock Input 11 = Reserved
6.3.18.3
* * * *
Configure GPIOB5 (GPS_B5)--Bits 12-11
This field selects the alternate function for GPIOB5.
00 = TA1 - Timer A1 (default) 01 = FAULT3 - PWM FAULT3 Input 10 = CLKIN - External Clock Input 11 = Reserved
6.3.18.4
Reserved--Bits 10-8
This bit field is reserved. Each bit must be set to 0.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 99
6.3.18.5
* * * *
Configure GPIOB3 (GPS_B3)--Bits 7-6
This field selects the alternate function for GPIOB3.
00 = MOSI0 - QSPI0 Master Out/Slave In (default) 01 = TA3 - Timer A3 10 = PSRC1 - PWM2/PWM3 Pair External Source 11 = Reserved
6.3.18.6
* * * *
Configure GPIOB2 (GPS_B2)--Bits 5-4
This field selects the alternate function for GPIOB2.
00 = MISO0 QSPI0 Master In/Slave Out (default) 01 = TA2 - Timer A2 10 = PSRC0 - PWM0/PWM1 Pair External Source 11 = Reserved
6.3.18.7 6.3.18.8
* *
Reserved--Bit 3 Configure GPIOB1 (GPS_B1)--Bit 2
This bit field is reserved. It must be set to 0.
This field selects the alternate function for GPIOB1.
0 = SS0 - QSPI0 Slave Select (default) 1 = SDA - I2C Serial Data
6.3.18.9
Reserved--Bit 1
This bit field is reserved. It must be set to 0.
6.3.18.10 Configure GPIOB0 (GPS_B0)--Bits 0
This field selects the alternate function for GPIOB0.
* * 0 = SCLK0 - QSPI0 Serial Clock (default) 1 = SCL - I2C Serial Clock
6.3.19
SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $16 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
GPS_ B11 0
7
0
6
GPS_ B10 0
5
0
4
0
3
0
2
0
1
0
0
GPS_ B7 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
56F8035/56F8025 Data Sheet, Rev. 6 100 Freescale Semiconductor
Register Descriptions
6.3.19.1 6.3.19.2
* *
Reserved--Bits 15-9 Configure GPIOB11 (GPS_B11)--Bit 8
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate function for GPIOB11.
0 = CMPBO - Comparator B Output (default) 1 = Reserved
6.3.19.3 6.3.19.4
* *
Reserved--Bit 7 Configure GPIOB10 (GPS_B10)--Bit 6
This bit field is reserved. It must be set to 0.
This field selects the alternate function for GPIOB10.
0 = CMPAO - Comparator A Output (default) 1 = Reserved
6.3.19.5 6.3.19.6
* *
Reserved--Bits 5-1 Configure GPIOB7 (GPS_B7)--Bit 0
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate function for GPIOB7.
0 = TXD0 - QSCI0 Transmit Data (default) 1 = SCL - I2C Serial Clock
6.3.20
SIM GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $17 Read Write RESET
15
0
14
0
13
0
12
GPS_ D5 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)
6.3.20.1 6.3.20.2
Reserved--Bits 15-13 Configure GPIOD5 (GPS_D5)--Bit 12
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate function for GPIOD5.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 101
* *
0 = XTAL - External Crystal Oscillator Output (default) 1 = CLKIN - External Clock Input
6.3.20.3
Reserved--Bits 11-0
This bit field is reserved. Each bit must be set to 0.
6.3.21
Internal Peripheral Source Select Register 0 for Pulse Width Modulator (SIM_IPS0)
The internal integration of peripherals provides input signal source selection for peripherals where an input signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral type and provide a selection list for every peripheral input signal that has more than one alternative source to indicate which source is selected. If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control of the I/O.
GPIOA5_PEREN Register GPIOA5 PWM5 00 0 PWM FAULT2 1 Comparator A Output (Internal) Timer A3 01 10 1
SIM_GPSA0 Register SIM_IPS0 Register
0 GPIOA5 pin
Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control IPSn settings should not be altered while an affected peripheral is in an enabled (operational) configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details.
56F8035/56F8025 Data Sheet, Rev. 6 102 Freescale Semiconductor
Register Descriptions
Base + $18 Read Write RESET
15
0
14
0
13
IPS0_ FAULT2 0
12
0
11
IPS0_ FAULT1 0
10
0
9
0
8
7
IPS0_PSRC2
6
5
4
IPS0_PSRC1
3
2
1
IPS0_PSRC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0)
6.3.21.1 6.3.21.2
* *
Reserved--Bits 15-14 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)--Bit 13
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed PWM input FAULT2.
0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default) 1 = CMPBO (Internal) - Use Comparator B Output
6.3.21.3 6.3.21.4
* *
Reserved--Bit 12 Select Input Source for FAULT1 (IPS0_FAULT1)--Bit 11
This bit field is reserved. It must be set to 0.
This field selects the alternate input source signal to feed PWM input FAULT1.
0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default) 1 = CMPAO (Internal) - Use Comparator A Output
6.3.21.5 6.3.21.6
Reserved--Bits 10-9 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)--Bits 8-6
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed PWM input PSRC2 as the PWM4/PWM5 pair source.
* * * 000 = Reserved (default) 001 = TA3 (Internal) - Use Timer A3 output as PWM source 010 = ADC SAMPLE2 (Internal) - Use ADC SAMPLE2 result as PWM source -- If the ADC conversion result in SAMPLE2 is greater than the value programmed into the High Limit register HLMT2, then PWM4 is set to 0 and PWM5 is set to 1 -- If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0 * * 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 103
* *
11x = Reserved 1x1 = Reserved
6.3.21.7
Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)--Bits 5-3
This field selects the alternate input source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair source.
* * * 000 = I/O pin (External) - Use a PSRC1 input pin as PWM source (default) 001 = TA2 (Internal) - Use Timer A2 output as PWM source 010 = ADC SAMPLE1 (Internal) - Use ADC SAMPLE1 result as PWM source -- If the ADC conversion result in SAMPLE1 is greater than the value programmed into the High Limit register HLMT1, then PWM2 is set to 0 and PWM3 is set to 1 -- If the ADC conversion result in SAMPLE1 is less than the value programmed into the Low Limit register LLMT1, then PWM2 is set to 1 and PWM3 is set to 0 * * * * 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source 11x = Reserved 1x1 = Reserved
6.3.21.8
Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)--Bits 2-0
This field selects the alternate input source signal to feed PWM input PSRC0 as the PWM0/PWM1 pair source.
* * * 000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default) 001 = TA0 (Internal) - Use Timer A0 output as PWM source 010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source -- If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit register HLMT0, then PWM0 is set to 0 and PWM1 is set to 1 -- If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit register LLMT0, then PWM0 is set to 1 and PWM1 is set to 0 * * * * 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source 11x = Reserved 1x1 = Reserved
6.3.22
Internal Peripheral Source Select Register 1 for Digital-to-Analog Converters (SIM_IPS1)
See Section 6.3.21 for general information about Internal Peripheral Source Select registers.
56F8035/56F8025 Data Sheet, Rev. 6 104 Freescale Semiconductor
Register Descriptions
Base + $19 Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
IPS1_DSYNC1
4
3
0
2
1
0
IPS1_DSYNC0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)
6.3.22.1 6.3.22.2
* * * * * * *
Reserved--Bits 15-7 Select Input Source for SYNC Input to DAC 1 (IPS1_DSYNC1)--Bits 6-4
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed DAC1 SYNC input.
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default) 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input 100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input 11x = Reserved
6.3.22.3 6.3.22.4
Reserved--Bit 3 Select Peripheral Input Source for SYNC Input to DAC 0 (IPS1_DSYNC0)--Bits 2-0
This bit field is reserved. It must be set to 0.
This field selects the alternate input source signal to feed DAC0 SYNC input.
* * * * * * * 000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default) 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input 100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input 11x = Reserved
6.3.23
Internal Peripheral Source Select Register 2 for Quad Timer A (SIM_IPS2)
See Section 6.3.21 for general information about Internal Peripheral Source Select registers.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 105
Base + $1A Read Write RESET
15
0
14
0
13
0
12
IPS2_ TA3 0
11
0
10
0
9
0
8
IPS2_ TA2 0
7
0
6
0
5
0
4
IPS2_ TA1 0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
6.3.23.1 6.3.23.2
* *
Reserved--Bits 15-13 Select Input Source for TA3 (IPS2_TA3)--Bit 12
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed Quad Timer A, input 3.
0 = I/O pin (External) - Use Timer A3 input/output pin 1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
6.3.23.3 6.3.23.4
* *
Reserved--Bits 11-9 Select Input Source for TA2 (IPS2_TA2)--Bit 8
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed Quad Timer A, input 2.
0 = I/O pin (External) - Use Timer A2 input/output pin 1 = CMPBO (Internal) - Use Comparator B output
6.3.23.5 6.3.23.6
* *
Reserved--Bits 7-5 Select Input Source for TA1 (IPS2_TA1)--Bit 4
This bit field is reserved. Each bit must be set to 0.
This field selects the alternate input source signal to feed Quad Timer A, input 1.
0 = I/O pin (External) - Use Timer A1 input/output pin 1 = CMPAO (Internal) - Use Comparator A output
6.3.23.7
Reserved--Bits 3-0
This bit field is reserved. Each bit must be set to 0. For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A module must be identical, at either the system clock rate or 3X system clock rate.
6.4 Clock Generation Overview
The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to produce a system clock at a maximum of 32MHz for the peripheral, core, and memory. It divides the
56F8035/56F8025 Data Sheet, Rev. 6 106 Freescale Semiconductor
Clock Generation Overview
master clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and can be an optional clock for PWM, Timer A, Timer B, and I2C modules. These clocks are generated by gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls. The OCCS configuration controls the operating frequency of the SIM's master clocks. In the OCCS, either an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz using ROSB), or powered down (using ROPD). An 8MHz MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master clocks to the SIM. When the PLL is selected, both the 3X system clock and the 2X system clock are enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC. In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables, and clock rate controls to provide flexible control of clocking and power utilization. The clock rate controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM, but requires the PLL to be on and selected. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. The peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 107
6.5 Power-Saving Modes
The 56F8035/56F8025 operates in one of five Power-Saving modes, as shown in Table 6-2.
Table 6-2 Clock Operation in Power-Saving Modes
Mode Run Wait Core Clocks Core and memory clocks enabled Core and memory clocks disabled Peripheral Clocks Peripheral clocks enabled Peripheral clocks enabled Description Device is fully functional Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2. Executing a Debug mode entry command during the 56800E core JTAG interface 3. Any reset (POR, external, software, COP) Core executes STOP instruction to enter this mode. Possible recoveries from Stop mode to Run mode are: 1. Interrupt from any peripheral configured in the CTRL register to operate in Stop mode (TA0-3, QSCI0, PIT0-1, CAN, CMPA-B) 2. Low-voltage interrupt 3. Executing a Debug mode entry command using the 56800E core JTAG interface 4. Any reset (POR, external, software, COP) The user configures the OCCS and SIM to select the relaxation oscillator clock source (PRECS), shut down the PLL (PLLPD), put the relaxation oscillator in Standby mode (ROSB), and put the large regulator in Standby (LRSTDBY). The device is fully operational, but operating at a minimum frequency and power configuration. Recovery requires reversing the sequence used to enter this mode (allowing for PLL lock time). The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset
Stop
Master clock generation in the OCCS remains operational, but the SIM disables the generation of system and peripheral clocks.
Standby
The OCCS generates the master clock at a reduced frequency (400kHz). The PLL is disabled and the high-speed peripheral option is not available. System and peripheral clocks operate at 200kHz.
Power-Down
Master clock generation in the OCCS is completely shut down. All system and peripheral clocks are disabled.
The power-saving modes provide additional power management options by disabling the clock, reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2. Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the
56F8035/56F8025 Data Sheet, Rev. 6 108 Freescale Semiconductor
Resets
default behavior of Stop mode. By asserting a peripheral's Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction. A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the device and minimizes its power utilization but is only recoverable via reset. When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator. All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system clock for PWM, Timers, and I2C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of operation is 32MHz.
6.6 Resets
The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). The three synchronous sources are the software reset (SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, the COP time-out reset (COP_TOR), and the COP loss-of-reference reset (COP_LOR). The reset generation module has three reset detectors, which resolve into four primary resets. These are outlined in Table 6-3. The JTAG circuitry is reset by the Power-On Reset. Table 6-3 Primary System Resets
Reset Sources Reset Signal EXTENDED_POR POR X External Software COP Comments Stretched version of POR released 64 OSC_CLK cycles after POR deasserts X X X Released 32 OSC_CLK cycles after all reset sources, including EXTENDED_POR, have released Releases 32 SYS_CLK cycles after the CLKGEN_RST is released Releases 32 SYS_CLK cycles after PERIP_RST is released
CLKGEN_RST
X
PERIP_RST
X
X
X
X
CORE_RST
X
X
X
X
Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 109
EXTENDED_POR JTAG
POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock CLKGEN_RST OCCS Memory Subsystem
COMBINED_RST External RESET IN (active low) RESET Delay 32 OSC_CLK Clock pulse shaper COP_TOR (active low) SW Reset COP_LOR (active low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles. Delay 32 sys clocks pulse shaper Delay 32 sys clocks pulse shaper CORE_RST 56800E PERIP_RST Peripherals
Figure 6-28 Sources of RESET Functional Diagram (Test modes not included) POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset from when power comes on to when code is running is 28S. An external reset generation circuit may also be used. A description of how these resets are used to initialize the clocking system and system modules is included in Section 6.7.
6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum), with the exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option to operate at 3X system clock. The SIM is responsible for clock distributions. While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module.
56F8035/56F8025 Data Sheet, Rev. 6 110 Freescale Semiconductor
Clocks
The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps:
1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an additional time period for the clock source and power to stabilize. 3. A Combined reset consists of the OR of the extended POR reset, the external reset, the COP reset and Software reset. The entire device, except for the POR extender, is held reset as long as Combined reset is asserted. The release of Combined reset permits operation of the CTRL register, the Synchronous reset generator, and the CLKGEN reset extender. 4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This provides a reasonable minimum duration to the reset for these specialized functions. 5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a window in which the SIM stabilizes the master clock inputs to the clock generator. 6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32 SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic remain clocked, but in reset, so that synchronous resets can be resolved. 7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender. The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the Peripheral reset. This provides a window in which critical peripheral start-up functions, such as Flash Security in the Flash memory, can be implemented. 8. The release of Core reset permits execution of code by the 56800E core and marks the end of the system start-up sequence.
Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external reset, COP and Software reset). In the 56F8035/56F8025, this signal will be stretched by the SIM for a period of time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 111
Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension
RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Switch on falling SYS_CLK
Figure 6-29 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8025 offers security features intended to prevent unauthorized users from reading the contents of the flash memory (FM) array. The 56F8025's flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the flash array. After flash security is set, an authorized user is still able to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via serial communication peripherals, is included in the application software.
7.1 Operation with Security Enabled
After the user has programmed flash with the application code, the 56F8025 can be secured by programming the security word $0002 into program memory location $00 7FF7. This non-volatile word will keep the device secured through reset and through power-down of the device. Refer to the flash memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the details. When flash
56F8035/56F8025 Data Sheet, Rev. 6 112 Freescale Semiconductor
Flash Access Lock and Unlock Mechanisms
security mode is enabled, the 56F8025 will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
There are several methods that effectively lock or unlock the on-chip flash.
7.2.1
Disabling EOnCE Access
On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip's boundary scan capability and access to the ID register, but proper implementation of flash security will block any attempt to access the internal flash memory via the EOnCE port when security is enabled.
7.2.2
Flash Lockout Recovery Using JTAG
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire contents of the user's secured code stored in flash are erased before security is disabled on the device on the next reset or power-up sequence. To start the lockout recovery sequence via JTAG, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller's instruction register. Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the 56F802x and 56F803x Peripheral Reference Manual for more details, or contact Freescale.
Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller and device to return to normal unsecured operation. Power-on reset will reset both too.
7.2.3
Flash Lockout Recovery using CodeWarrior
CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device's memory configuration file. The command "Unlock_Flash_on_Connect 1" in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared).
7.2.4
Flash Lockout Recovery without mass erase
A user can un-secure a secured device by programming the word $0000 into program memory location $00 7FF7. After completing the programming, both the JTAG TAP controller and the device must be reset
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 113
in order to return to normal unsecured operation. Power-on reset will also reset both. The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces.
Note: Flash contents can only be programmed for 1s to 0s.
7.3 Product Analysis
The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in section 7.2.4. The customer would need to supply Technical Support with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not program the security word.
Part 8 General-Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F802x and 56F803x Peripheral Reference Manual and contains only chip-specific information. This information supersedes the generic information in the 56F802x and 56F803x Peripheral Reference Manual.
8.2 Configuration
There are four GPIO ports defined on the 56F8035/56F8025. The width of each port, the associated peripheral, and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2. Additional details are shown in Tables 2-2 and 2-3.
Table 8-1 GPIO Ports Configuration
Available Pins in 56F8035/56F 8025 12 9
GPIO Port
Peripheral Function
Reset Function
A B
PWM, Timer, QSPI, Comparator, Reset QSPI, I2C, PWM, Clock, Comparator, Timer ADC, Comparator, QSCI Clock, Oscillator, DAC, JTAG
GPIO, RESET GPIO
C D
8 6
GPIO GPIO, JTAG
56F8035/56F8025 Data Sheet, Rev. 6 114 Freescale Semiconductor
Configuration
Table 8-2 GPIO External Signals Map
GPIO Function
GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4
Peripheral Function
PWM0 PWM1 PWM2 PWM3 PWM4 / TA2 / FAULT1
LQFP Package Pin 40 39 32 33 31 Defaults to A0 Defaults to A1 Defaults to A2 Defaults to A3
Notes
SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2. Defaults to A5 SIM register SIM_GPS is used to select between FAULT0 and TA0. Defaults to A6 Defaults to RESET SIM register SIM_GPS is used to select between FAULT1, TA2, and CMPAI1. Defaults to A8 SIM register SIM_GPS is used to select between FAULT2, TA3, and CMPBI1. Defaults to A9 Defaults to A10 Defaults to A11 SIM register SIM_GPS is used to select between SCLK and SCL. Defaults to B0 SIM register SIM_GPS is used to select between SS0 and SDA. Defaults to B1 SIM register SIM_GPS is used to select between MISO0, TA2, and PSRC0. Defaults to B2
GPIOA5
PWM5 / TA3 / FAULT2
27
GPIOA6
FAULT0 / TA0
24
GPIOA7 GPIOA8
RESET FAULT1 / TA2 / CMPAI1
21 26
GPIOA9
FAULT2 / TA3 / CMPBI1
5
GPIOA10 GPIOA11 GPIOB0
CMPAI2 CMPBI2 SCLK0 / SCL
25 6 30
GPIOB1
SS0 / SDA
2
GPIOB2
MISO0 / TA2 / PSRC0
23
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 115
Table 8-2 GPIO External Signals Map (Continued)
GPIO Function
GPIOB3
Peripheral Function
MOSI0 / TA3 / PSRC1
LQFP Package Pin 22
Notes SIM register SIM_GPS is used to select between MOSI0, TA3 and PSRC1. Defaults to B3 SIM register SIM_GPS is used to select between TA1, FAULT3, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B5 SIM register SIM_GPS is used to select between RXD0, SDA, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B6 SIM register SIM_GPS is used to select between TXD0 and SCL. Defaults to B7 Defaults to B10 Defaults to B11 SIM register SIM_GPS is used to select between ANA0 and CMPAI3. Defaults to C0 Defaults to C1 SIM register SIM_GPS is used to select between ANA2 and VREFHA. Defaults to C2 SIM register SIM_GPS is used to select between ANA3 and VREFLA. Defaults to C3 SIM register SIM_GPS is used to select between ANB0 and CMPBI3. Defaults to C4 Defaults to C5 SIM register SIM_GPS is used to select between ANB2 and VREFHB. Defaults to C6 SIM register SIM_GPS is used to select between ANB3 and VREFLB. Defaults to C7
GPIOB5
TA1 / FAULT3 / CLKIN
4
GPIOB6
RXD0 / SDA / CLKIN
1
GPIOB7
TXD0 / SCL
3
GPIOB10 GPIOB11 GPIOC0
CMPAO CMPBO ANA0 / CMPAI3
20 42 16
GPIOC1 GPIOC2
ANA1 ANA2 / VREFHA
15 14
GPIOC3
ANA3 / VREFLA
13
GPIOC4
ANB0 / CMPBI3
7
GPIOC5 GPIOC6
ANB1 ANB2 / VREFHB
8 9
GPIOC7
ANB3 / VREFLB
10
56F8035/56F8025 Data Sheet, Rev. 6 116 Freescale Semiconductor
Reset Values
Table 8-2 GPIO External Signals Map (Continued)
GPIO Function
GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5
Peripheral Function
TDI TDO TCK TMS EXTAL XTAL / CLKIN
LQFP Package Pin 41 44 19 43 38 37 Defaults to TDI Defaults to TDO Defaults to TCK Defaults to TMS Defaults to D4
Notes
SIM register SIM_GPSCD is used to select between XTAL and CLKIN. Defaults to D5
8.3 Reset Values
Tables 8-1 and 8-2 detail registers for the 56F8035/56F8025; Figures 8-1 through 8-4 summarize register maps and reset values.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 117
Add. Offset
Register Acronym R W RS R W RS
15 0 0
14 0 1
13 0 1
12 0 1
11
10
9
8
7
6
5
4
3
2
1
0
$0
GPIOA_PUPEN
PU[15:0] 1 1 1 1 1 1 1 1 1 1 1 1
.0
0
.0
0
.0
0
.0
0 0 0 0 0 0
$1
GPIOA_DATA
D[15:0] 0 0 0 0 0 0 0
$2
GPIOA_DDIR
R .0. W RS 0 R W RS R W RS R W RS R W RS R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
.0.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
.0.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
.0.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0 0 0 0 0 0 X X X X 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DD[15:0] 0 0 0 0 0 0 0
$3
GPIOA_PEREN
PE[15:0] 0 0 0 0 0 0 0
$4
GPIOA_IASSRT
IA[15:0] 0 0 0 0 0 0 0
$5
GPIOA_IEN
IEN[15:0] 0 0 0 0 0 0 0
$6
GPIOA_IEPOL
IEPOL[15:0] 0 0 0 0 0 0 0
IPR[15:0] 0 0 0 0 0 0 0
$7
GPIOA_IPEND
W RS R W RS R W RS R W RS R W RS R W RS
$8
GPIOA_IEDGE
IES[15:0] 0 0 0 0 0 0 0
$9
GPIOA_PPOUTM
OEN[15:0] 1 1 1 1 1 1 1
RAW DATA[15:0] X X X X X X X X
$A
GPIOA_RDATA
$B
GPIOA_DRIVE
DRIVE[15:0] 0 0 0 0 0 0 0
Read as 0 Reserved Reset
Figure 8-1 GPIOA Register Map Summary
56F8035/56F8025 Data Sheet, Rev. 6 118 Freescale Semiconductor
Reset Values
Add. Offset
Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
11
10
9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
7
6
5
4 0
3
2
1
0
$0
GPIOB_PUPEN
PU[15:0] 1 1
PU 1 1 D 0 0 DD 0 0 PE 0 0 IA 0 0 IEN 0 0 IEPOL 0 0 IPR 0 0 IES 0 0 OEN 1 1 1 0 0 0 0 0 0 0 0 1
PU 1 1 D 0 0 DD 0 0 PE 0 0 IA 0 0 IEN 0 0 0 0 0 0 0 0 0 0 0 0 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0
$1
GPIOB_DATA
D[15:0] 0 0
$2
GPIOB_DDIR
DD[15:0] 0 0
$3
GPIOB_PEREN
PE[15:0] 0 0
$4
GPIOB_IASSRT
IA[15:0] 0 0
$5
GPIOB_IEN
IEN[15:0] 0 0
$6
GPIOB_IEPOL
IEPOL[15:0] 0 0
IEPOL 0 0 IPR 0 0 IES 0 0 0 OEN 1 1 1 1 0 0 0 0 0
IPR[15:0] 0 0
$7
GPIOB_IPEND
$8
GPIOB_IEDGE
IES[15:0] 0 0
$9
GPIOB_PPOUTM
OEN[15:0] 1 1
$A
GPIOB_RDATA
RAW DATA[15:0] X X
RAW DATA X X DRIVE 0 0 0 X
RAW DATA X X X X
W RS R W RS R W RS
$B
GPIOB_DRIVE
DRIVE[15:0] 0 0
DRIVE 0 0 0 0
0
Read as 0 Reserved Reset
Figure 8-2 GPIOB Register Map Summary
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 119
Add. Offset
Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R
15 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0 0
14 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
13 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
10 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X 0 0
7
6
5
4
3
2
1
0
$0
GPIOC_PUPEN
PU[15:0] 1 1 1 1 1 1 1 1
$1
GPIOC_DATA
D[15:0] 0 0 0 0 0 0 0 0
$2
GPIOC_DDIR
DD[15:0] 0 0 0 0 0 0 0 0
$3
GPIOC_PEREN
PE[15:0] 0 0 0 0 0 0 0 0
$4
GPIOC_IASSRT
IA[15:0] 0 0 0 0 0 0 0 0
$5
GPIOC_IEN
IEN[15:0] 0 0 0 0 0 0 0 0
$6
GPIOC_IEPOL
IEPOL[15:0] 0 0 0 0 0 0 0 0
IPR[15:0] 0 0 0 0 0 0 0 0
$7
GPIOC_IPEND
W RS R W RS R W RS R W RS R W RS R W RS
$8
GPIOC_IEDGE
IES[15:0] 0 0 0 0 0 0 0 0
$9
GPIOC_PPOUTM
OEN[15:0] 1 1 1 1 1 1 1 1
RAW DATA[15:0] X X X X X X X X
$A
GPIOC_RDATA
$B
GPIOC_DRIVE
DRIVE[15:0] 0 0 0 0 0 0 0 0
Read as 0 Reserved Reset
Figure 8-3 GPIOC Register Map Summary
56F8035/56F8025 Data Sheet, Rev. 6 120 Freescale Semiconductor
Reset Values
Add. Offset
Register Acronym R W RS R W RS R W RS R W RS R W RS R W RS R W RS R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
$0
GPIOD_PUPEN
PU[15:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
$1
GPIOD_DATA
D[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$2
GPIOD_DDIR
DD[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$3
GPIOD_PEREN
PE[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
$4
GPIOD_IASSRT
IA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$5
GPIOD_IEN
IEN[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$6
GPIOD_IEPOL
IEPOL[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IPR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$7
GPIOD_IPEND
W RS R W RS R W RS R W RS R W RS R W RS
$8
GPIOD_IEDGE
IES[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$9
GPIOD_PPOUTM
OEN[15:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RAW DATA[15:0] 0 0 0 0 0 0 0 0 X X X X X X X X
$A
GPIOD_RDATA
$B
GPIOD_DRIVE
DRIVE[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read as 0 Reserved Reset
Figure 8-4 GPIOD Register Map Summary
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 121
Part 9 Joint Test Action Group (JTAG)
9.1 56F8035/56F8025 Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual.
Part 10 Specifications
10.1 General Characteristics
The 56F8035/56F8025 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term "5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40C to 125C ambient temperature over the following supply ranges: VSS = VSSA = 0V, VDD = VDDA = 3.0-3.6V, CL < 50pF, fOP = 32MHz
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56F8035/56F8025 Data Sheet, Rev. 6 122 Freescale Semiconductor
General Characteristics
Table 10-1 Absolute Maximum Ratings
(VSS = 0V, VSSA = 0V) Characteristic Supply Voltage Range Analog Supply Voltage Range ADC High Voltage Reference Voltage difference VDD to VDDA Voltage difference VSS to VSSA Digital Input Voltage Range Oscillator Voltage Range Analog Input Voltage Range Input clamp current, per pin (VIN < 0)1 Output clamp current, per pin (VO < 0)1 Output Voltage Range (Normal Push-Pull mode) Output Voltage Range (Open Drain mode) Ambient Temperature Industrial Storage Temperature Range (Extended Industrial)
1. Continuous clamp current per pin is -2.0 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL
Symbol VDD VDDA VREFHx VDD VSS VIN VOSC VINA VIC VOC VOUT VOUTOD
Notes
Min -0.3 - 0.3 - 0.3 - 0.3 - 0.3
Max 4.0 4.0 4.0 0.3 0.3 6.0 4.0 4.0 -20.0 -20.0 4.0 6.0
Unit V V V V V V V V mA mA V V
Pin Groups 1, 2 Pin Group 4 Pin Group 3
- 0.3 - 0.4 - 0.3 -- --
Pin Group 1
- 0.3 - 0.3
Pin Group 2
TA TSTG
- 40 - 55
105 150
C C
10.1.1
ElectroStatic Discharge (ESD) Model
Table 10-2 56F8035/56F8025 ESD Protection
Characteristic ESD for Human Body Model (HBM) Min 2000 Typ -- Max -- Unit V
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 123
Table 10-2 56F8035/56F8025 ESD Protection
Characteristic ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Min 200 750 Typ -- -- Max -- -- Unit V V
Table 10-3 LQFP Package Thermal Characteristics6
Characteristic Junction to ambient Natural convection Junction to ambient Natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to package top Natural Convection
Comments
Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p)
Symbol
Value (LQFP) 41 34
Unit
Notes
RJA RJMA RJMA RJMA RJB RJC JT
C/W C/W
2 1, 2
34
C/W
2
29
C/W
1, 2
24 8 2
C/W C/W C/W
4 3 5
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction to ambient thermal resistance, Theta-JA (RJA), was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where "s" is the number of signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case thermal resistance, Theta-JC (RJC), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Junction to board thermal resistance, Theta-JB (RJB), is a metric of the thermal resistance from the junction to the printed circuit board determined per JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal Characterization Parameter, Psi-JT (YJT), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. YJT is a useful value to use to estimate junction temperature in steady state customer environments. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. See Section 12.1 for more details on thermal design considerations.
56F8035/56F8025 Data Sheet, Rev. 6 124 Freescale Semiconductor
General Characteristics
Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V)
Characteristic Supply voltage ADC Reference Voltage High Voltage difference VDD to VDDA Voltage difference VSS to VSSA Device Clock Frequency Using relaxation oscillator Using external clock source Input Voltage High (digital inputs) Input Voltage Low (digital inputs) Oscillator Input Voltage High XTAL driven by an external clock source Oscillator Input Voltage Low Output Source Current High at VOH min.)1 When programmed for low drive strength When programmed for high drive strength Output Source Current Low (at VOL max.)1 When programmed for low drive strength When programmed for high drive strength Ambient Operating Temperature (Extended Industrial) Flash Endurance (Program Erase Cycles) Flash Data Retention Flash Data Retention with <100 Program/Erase Cycles Symbol VDD, VDDA VREFHx VDD VSS FSYSCLK 1 0 VIH VIL VIHOSC VILOSC IOH Pin Group 1 Pin Group 1 IOL Pin Groups 1, 2 Pin Groups 1, 2 TA NF TR tFLRET TA = -40C to 125C TJ <= 85C avg TJ <= 85C avg -- -- -40 10,000 15 20 -- 4 8 105 -- -- -- mA C cycles years years -- -- -4 -8 mA Pin Groups 1, 2 Pin Groups 1, 2 Pin Group 4 Pin Group 4 2.0 -0.3 2.0 -0.3 32 32 5.5 0.8 VDDA + 0.3 0.8 MHz V V V V Notes Min 3 3.0 -0.1 -0.1 0 0 Typ 3.3 Max 3.6 VDDA 0.1 0.1 Unit V V V V
1. Total chip source or sink current cannot exceed 75mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 125
10.2 DC Electrical Characteristics
Table 10-5 DC Electrical Characteristics
At Recommended Operating Conditions
Characteristic Output Voltage High Output Voltage Low Digital Input Current High (a) pull-up enabled or disabled Comparator Input Current High Oscillator Input Current High Digital Input Current Low1 pull-up enabled pull-up disabled Comparator Input Current Low Oscillator Input Current Low DAC Output Voltage Range Symbol VOH VOL IIH IIHC IIHOSC IIL Notes Pin Group 1 Pin Groups 1, 2 Pin Groups 1, 2 Min 2.4 -- -- Typ -- -- 0 Max -- 0.4 +/- 2.5 Unit V V A A A A -15 -- IILC IILOSC VDAC Pin Group 3 Pin Group 3 Internal -- -- Typically VSSA + 40mV -- -30 0 0 0 -- -60 +/- 2.5 +/- 2 +/- 2 Typically VDDA 40mV +/- 2.5 A A V VIN = 0V VIN = 0V -- Test Conditions IOH = IOHmax IOL = IOLmax VIN = 2.4V to 5.5V VIN = VDDA VIN = VDDA VIN = 0V
Pin Group 3 Pin Group 3 Pin Groups 1, 2
-- --
0 0
+/- 2 +/- 2
Output Current 1 High Impedance State Schmitt Trigger Input Hysteresis Input Capacitance Output Capacitance 1. See Figure 10-1
Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7
IOZ VHYS CIN COUT
Pin Groups 1, 2
0
A V pF pF
--
Pin Groups 1, 2
-- -- --
0.35 10 10
-- -- --
-- -- --
Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL
56F8035/56F8025 Data Sheet, Rev. 6 126 Freescale Semiconductor
DC Electrical Characteristics
2.0 0.0 - 2.0 A - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Volt 3.5 4.0 4.5 5.0 5.5 6.0
Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled)
Table 10-6 Current Consumption per Power Supply Pin
Typical @ 3.3V, 25C Maximum@ 3.6V, 25C IDD1 -- IDDA --
Mode
Conditions
IDD1 IDDA 18.8mA
RUN
32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled. TMR and PWM using 1X Clock ADC/DAC powered on and clocked Comparator powered on 32MHz Device Clock Relaxation Oscillator on PLL powered on Processor Core in WAIT state All Peripheral modules enabled. TMR and PWM using 1X Clock ADC/DAC/Comparator powered off 4MHz Device Clock Relaxation Oscillator on PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off
48mA
WAIT
29mA
0A
--
--
STOP
5.4mA
0A
--
--
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 127
Table 10-6 Current Consumption per Power Supply Pin (Continued)
Typical @ 3.3V, 25C Maximum@ 3.6V, 25C IDD1 650A IDDA 1A
Mode
Conditions
IDD1 IDDA 0A
STANDBY > STOP
100kHz Device Clock Relaxation Oscillator in Standby mode PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off Voltage regulator in Standby mode Device Clock is off Relaxation Oscillator powered off PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC /DAC/Comparator powered off Voltage Regulator in Standby mode
540A
POWERDOWN
440A
0A
550A
1A
1. No Output Switching All ports configured as inputs All inputs Low No DC Loads
Table 10-7 Power-On Reset Low-Voltage Parameters
Characteristic
Low-Voltage Interrupt for 3.3V supply1 Low-Voltage Interrupt for 2.5V supply2 Low-Voltage Interrupt Recovery Hysteresis Power-On Reset3
Symbol
VEI3.3 VE12.5 VEIH POR
Min 2.58 -- -- --
Typ 2.7 2.15 50 1.8
Max -- -- -- 1.9
Unit V V mV V
1. When VDD drops below VEI3.3, an interrupt is generated. 2. When VDD drops below VEI32.5, an interrupt is generated. 3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V 1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.
10.2.1
Voltage Regulator Specifications
The 56F8035/56F8025 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has no external pins and therefore has no external characteristics which must be guaranteed (other than proper operation of the device). The second regulator supplies approximately 2.5V to the 56F8035/56F8025's core logic. This regulator requires an external 4.4F, or greater, capacitor for proper operation. Ceramic
56F8035/56F8025 Data Sheet, Rev. 6 128 Freescale Semiconductor
AC Electrical Characteristics
and tantalum capacitors tend to provide better performance tolerances. The output voltage can be measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8.
Table 10-8. Regulator Parameters
Characteristic Short Circuit Current Short Circuit Tolerance (VCAP shorted to ground) Symbol ISS TRSC Min -- -- Typical 450 -- Max 650 30 Unit mA minutes
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-2.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 10-2 Input Signal Measurement References Figure 10-3 shows the definitions of the following signal states:
* * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3
Figure 10-3 Signal States
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 129
10.4 Flash Memory Characteristics
Table 10-9 Flash Timing Parameters
Characteristic Program time1 Erase time 2 Mass erase time Symbol Min 20 20 100 Typ -- -- -- Max 40 -- -- Unit s ms ms
Tprog Terase Tme
1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory.
10.5 External Clock Operation Timing
Table 10-10 External Clock Operation Timing Requirements1
Characteristic Frequency of operation (external clock driver)2 Clock Pulse Width3 External Clock Input Rise Time4 External Clock Input Fall Time5
1. Parameters listed are guaranteed by design. 2. See Figure 10-4 for details on using the recommended connection of an external clock driver. 3. The chip may not function if the high or low pulse width is smaller than 6.25ns. 4. External clock input rise time is measured from 10% to 90%. 5. External clock input fall time is measured from 90% to 10%.
Symbol fosc tPW trise tfall
Min 4 6.25 -- --
Typ 8 -- -- --
Max 8 -- 3 3
Unit MHz ns ns ns
VIH
External Clock
90% 50% 10%
90% 50% 10%
tPW Note: The midpoint is VIL + (VIH - VIL)/2.
tPW
tfall
trise
VIL
Figure 10-4 External Clock Timing
56F8035/56F8025 Data Sheet, Rev. 6 130 Freescale Semiconductor
Phase Locked Loop Timing
10.6 Phase Locked Loop Timing
Table 10-11 PLL Timing
Characteristic External reference crystal frequency for the PLL1 Internal reference relaxation oscillator frequency for the PLL PLL output frequency2 (24 x reference frequency) PLL lock time3 Accumulated jitter using an 8MHz external crystal as the PLL source4 Cycle-to-cycle jitter Symbol fosc frosc fop tplls JA tjitterpll Min 4 -- 96 -- -- -- Typ 8 8 192 40 -- 350 Max -- -- -- 100 0.37 -- Unit MHz MHz MHz s % ps
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input. 2. The core system clock will operate at 1/6 of the PLL output frequency. 3. This is the time required after the PLL is enabled to ensure reliable operation. 4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency and using an 8MHz oscillator frequency.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 131
10.7 Relaxation Oscillator Timing
Table 10-12 Relaxation Oscillator Timing
Characteristic Relaxation Oscillator output frequency1 Normal Mode Standby Mode Relaxation Oscillator stabilization time2 Cycle-to-cycle jitter. This is measured on the CLKO signal (programmed prescaler_clock) over 264 clocks3 Minimum tuning step size Maximum tuning step size Variation over temperature -40C to 150C4 Variation over temperature 0C to 105C4
1. Output frequency after factory trim value. 2. This is the time required from Standby to Normal mode transition. 3. JA is required to meet QSCI requirements. 4. See Figure 10-5
Symbol fop
Minimum --
Typical 8.05 200
Maximum --
Unit MHz kHz
troscs tjitterrosc
-- --
1 400
3 --
ms ps
-- -- -- --
.08 40
-- --
% % % %
+1.0 to -1.5 +3.0 to -3.0 0 to +1 +2.0 to -2.0
8.16
8.08
8 MHz 7.92 7.84 -50 -25 0 25 50 75 100 125 150 175
Degrees C (Junction)
Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim
56F8035/56F8025 Data Sheet, Rev. 6 132 Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
. Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic Minimum RESET Assertion Duration Minimum GPIO pin Assertion for Interrupt RESET deassertion to First Address Fetch3 Delay from Interrupt Assertion to Fetch of first instruction (exiting Stop) Symbol tRA tIW tRDA tIF Typical Min 4T 2T 96TOSC + 64T -- Typical Max -- -- 97TOSC + 65T 6T Unit ns ns ns ns See Figure -- 10-6 -- --
1. In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. 3. During Power-On Reset, it is possible to use the 56F8035/56F8025 internal reset stretching circuitry to extend this period to 2^21T.
GPIO pin (Input) TIW
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 133
10.9 Serial Peripheral Interface (SPI) Timing
Table 10-14 SPI Timing1
Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave Symbol tC 125 62.5 tELD -- 31 tELG -- 125 tCH 50 31 tCL 50 31 tDS 20 0 tDH 0 2 tA 4.8 tD 3.7 tDV -- -- tDI 0 0 tR -- -- tF -- -- 9.7 9.0 ns ns 11.5 10.0 ns ns -- -- ns ns 4.5 20.4 ns ns 15.2 ns 10-7, 10-8, 10-9, 10-10 10-7, 10-8, 10-9, 10-10 10-7, 10-8, 10-9, 10-10 10-7, 10-8, 10-9, 10-10 15 ns 10-10 -- -- ns ns -- -- ns ns -- -- ns ns 10-7, 10-8, 10-9, 10-10 10-7, 10-8, 10-9, 10-10 10-10 -- -- ns ns -- -- ns ns 10-7, 10-8, 10-9, 10-10 10-10 -- -- ns ns 10-10 -- -- ns ns Min Max Unit See Figure 10-7, 10-8, 10-9, 10-10 10-10
56F8035/56F8025 Data Sheet, Rev. 6 134 Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
1. Parameters listed are guaranteed by design.
SS
(Input)
SS is held High on master
tC tR tF
SCLK (CPOL = 0) (Output)
tCL tCH tF tCL
tR
SCLK (CPOL = 1) (Output)
tDH tDS
tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 10-7 SPI Master Timing (CPHA = 0)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 135
SS
(Input)
tC
SS is held High on master
tF tR
SCLK (CPOL = 0) (Output)
tCL tCH
tF
SCLK (CPOL = 1) (Output)
tCL tCH tDS tR tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 10-8 SPI Master Timing (CPHA = 1)
56F8035/56F8025 Data Sheet, Rev. 6 136 Freescale Semiconductor
Serial Peripheral Interface (SPI) Timing
SS
(Input)
tC tCL tR tF tELG
SCLK (CPOL = 0) (Input)
tELD
tCH
SCLK (CPOL = 1) (Input)
tA
tCL tCH
tR
tF
tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-9 SPI Slave Timing (CPHA = 0)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 137
SS
(Input)
tC tF tCL tCH tELD tCL tR
SCLK (CPOL = 0) (Input)
tELG
SCLK (CPOL = 1) (Input)
tDV tA tCH tF tR tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-10 SPI Slave Timing (CPHA = 1)
10.10 Quad Timer Timing
Table 10-15 Timer Timing1, 2
Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period Symbol PIN PINHL POUT POUTHL Min 2T + 6 1T + 3 125 50 Max -- -- -- -- Unit ns ns ns ns See Figure 10-11 10-11 10-11 10-11
1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns. 2. Parameters listed are guaranteed by design.
56F8035/56F8025 Data Sheet, Rev. 6 138 Freescale Semiconductor
Quad Timer Timing
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 10-11 Timer Timing
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 139
10.11 Serial Communication Interface (SCI) Timing
Table 10-16 SCI Timing1
Characteristic Baud Rate2 RXD3 Pulse Width TXD4 Pulse Width Symbol BR RXDPW TXDPW Min Max (fMAX/16) 1.04/BR 1.04/BR Unit Mbps ns ns See Figure
--
0.965/BR 0.965/BR LIN Slave Mode
--
10-12 10-13
Deviation of slave node clock from nominal clock rate before synchronization Deviation of slave node clock relative to the master node clock after synchronization Minimum break character length
FTOL_UNSYNCH
-14
14
%
--
FTOL_SYNCH
-2
2
%
--
TBREAK
13
--
Master node bit periods Slave node bit periods
--
11
1. Parameters listed are guaranteed by design.
--
--
2. fMAX is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8035/56F8025 device. 3. The RXD pin in QSCI0 is named RXD0. 4. The TXD pin in QSCI0 is named TXD0.
RXD QSCI Receive data pin (Input)
RXDPW
Figure 10-12 RXD Pulse Width
TXD QSCI Receive data pin (Input)
TXDPW
Figure 10-13 TXD Pulse Width
56F8035/56F8025 Data Sheet, Rev. 6 140 Freescale Semiconductor
Inter-Integrated Circuit Interface (I2C) Timing
10.12 Inter-Integrated Circuit Interface (I2C) Timing
Table 10-17 I2C Timing
Standard Mode Characteristic SCL Clock Frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time for I2C bus devices Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between STOP and START condition Pulse width of spikes that must be suppressed by the input filter Symbol Minimum fSCL tHD; STA 0 4.0 Maximum 100 -- Minimum 0 0.6 Maximum 400 -- kHz s Fast Mode Unit
tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tr tf tSU; STO tBUF
4.7 4.0 4.7 01 2503 -- -- 4.0 4.7
-- -- -- 3.452 -- 1000 300 -- --
1.23 0.6 0.6 01 1003, 4 20 +0.1Cb5 20 +0.1Cb5 0.6 1.3
-- -- -- 0.92 -- 300 300 -- --
s s s s ns ns ns s s
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 4. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT > = 250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250ns (according to the Standard mode I2C bus specification) before the SCL line is released. 5. Cb = total capacitance of the one bus line in pF
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 141
SDA
tf SCL
tLOW
tr
tSU; DAT
tf tHD; STA tSP
tr
tBUF
S
tHD; STA
tSU; STA tHD; DAT tHIGH
SR
tSU; STO
P
S
Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus
56F8035/56F8025 Data Sheet, Rev. 6 142 Freescale Semiconductor
JTAG Timing
10.13 JTAG Timing
Table 10-18 JTAG Timing
Characteristic TCK frequency of operation1 TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state Symbol fOP tPW tDS tDH tDV tTS Min DC 50 5 5 -- -- Max SYS_CLK/8 -- -- -- 30 30 Unit MHz ns ns ns ns ns See Figure 10-15 10-15 10-16 10-16 10-16 10-16
1. TCK frequency of operation must be less than 1/8 the processor rate.
1/fOP tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 10-15 Test Clock Input Timing Diagram
TCK (Input)
tDS tDH
TDI TMS (Input) TDO (Output)
Input Data Valid
tDV
Output Data Valid
tTS
TDO (Output)
Figure 10-16 Test Access Port Timing Diagram
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 143
10.14 Analog-to-Digital Converter (ADC) Parameters
Table 10-19 ADC Parameters1
Parameter DC Specifications Resolution ADC internal clock Conversion range ADC power-up time2 Recovery from auto standby Conversion time Sample time Accuracy Integral non-linearity4 (Full input signal range) Differential non-linearity Monotonicity Offset Voltage Internal Ref Offset Voltage External Ref Gain Error (transfer gain) ADC Inputs6 (Pin Group 3) Input voltage (external reference) Input voltage (internal reference) Input leakage VREFH current Input injection current7, per pin Input capacitance Input impedance AC Specifications Signal-to-noise ratio Total Harmonic Distortion Spurious Free Dynamic Range Signal-to-noise plus distortion Effective Number Of Bits
2. Includes power-up of ADC and VREF
Symbol
Min
Typ
Max
Unit
RES fADIC RAD tADPU tREC tADC tADS
12 0.1 VREFL -- -- -- --
-- -- -- 6 0 6 1
12 5.33 VREFH 13 1 -- --
Bits MHz V tAIC cycles3 tAIC cycles3 tAIC cycles3 tAIC cycles3 LSB5 LSB5 mV mV --
INL DNL
-- --
+/- 3 +/- .6 GUARANTEED
+/- 5 +/- 1
VOFFSET VOFFSET EGAIN
-- -- --
+/- 4 +/- 6 .998 to 1.002
+/- 9 +/- 12 1.01 to .99
VADIN VADIN IIA IVREFH IADI CADI XIN SNR THD SFDR SINAD ENOB
VREFL VSSA -- -- -- -- -- 60 60 61 58 --
-- -- 0 0 -- See Figure 10-17 See Figure 10-17 65 64 66 62 10.0
VREFH VDDA +/- 2 -- 3 -- --
V V A A mA pF Ohms dB dB dB dB Bits
1. All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
3. ADC clock cycles
4. INL measured from VIN = VREFL to VIN = VREFH
56F8035/56F8025 Data Sheet, Rev. 6 144 Freescale Semiconductor
Equivalent Circuit for ADC Inputs
5. LSB = Least Significant Bit = 0.806mV 6. Pin groups are detailed following Table 10-1. 7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC.
10.15 Equivalent Circuit for ADC Inputs
Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFHx - VREFLx) / 2, while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFHx - VREFLx) / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF, and the ADC clock frequency.
125 ESD Resistor 8pF noise damping capacitor Analog Input 3
S1 S3
4
C1 S/H C2 C1 = C2 = 1pF
1
2
(VREFHx - VREFL x) / 2
S2
1. 2. 3. 4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF Equivalent resistance for the channel select mux; 100 ohms Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pF
Figure 10-17 Equivalent Circuit for A/D Loading
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 145
10.16 Comparator (CMP) Parameters
Table 10-20 CMP Parameters
Characteristic Input Offset Voltage1 Conditions/Comments Within range of VDDA - .1V to VSSA + .1V Symbol VOFFSET Min -- Typ 10 Max 35 Unit mV
Input Propagation Delay Power-up time
1. No guaranteed specification within 0.1V of VDDA or VSSA
tPD tCPU
-- --
35 TBD
45 TBD
ns
10.17 Digital-to-Analog Converter (DAC) Parameters
Table 10-21 DAC Parameters
Parameter DC Specifications Resolution Conversion time Conversion rate Power-up time Time from release of PWRDWN signal until DACOUT signal is valid Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range > 6 sigma monotonicity, < 3.4 ppm non-monotonicity Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range Within 40mV of either VREFLX or VREFHX VOFFSET -- tDAPU 12 TBD TBD -- -- -- -- 12 2 500.000 11 bits S conv/sec S Conditions/Comments Symbol Min Typ Max Unit
Accuracy Integral non-linearity1 INL -- +/- 3 +/- 8.0 LSB2
Differential non-linearity1
DNL
--
+/- .8
<-1
LSB2
Monotonicity Offset error1
guaranteed +/- 25 +/- 40
-- mV
Gain error1
EGAIN
--
+/- .5
+/- 1.5
%
DAC Output Output voltage range VOUT VREFLX +.04V -- VREFHX - .04V V
56F8035/56F8025 Data Sheet, Rev. 6 146 Freescale Semiconductor
Digital-to-Analog Converter (DAC) Parameters
Table 10-21 DAC Parameters (Continued)
Parameter AC Specifications Signal-to-noise ratio Spurious free dynamic range Effective number of bits
1. No guaranteed specification within 5% of VDDA or VSSA 2. LSB = 0.806mV
Conditions/Comments
Symbol
Min
Typ
Max
Unit
SNR SFDR ENOB
-- -- 9
TBD TBD --
-- -- --
dB dB bits
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 147
10.18 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8035/56F8025. This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component] A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero Y-intercept.
Table 10-22 I/O Loading Coefficients at 10MHz
Intercept 8mA drive 4mA drive 1.3 1.15mW Slope 0.11mW / pF 0.11mW / pF
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 10-22 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load. In these cases: TotalPower = ((Intercept + Slope*Cload)*frequency/10MHz) where:
* * Summation is performed over all output pins with capacitive loads TotalPower is expressed in mW
56F8035/56F8025 Data Sheet, Rev. 6 148 Freescale Semiconductor
56F8035/56F8025 Package and Pin-Out Information
*
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.
Part 11 Packaging
11.1 56F8035/56F8025 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8035/56F8025. This device comes in a 44-pin Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline, Figure 11-2 shows the mechanical parameters and Table 11-1 lists the pin-out.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 149
GPIOB11 / CMPBO
TDO / GPIOD1
TMS / GPIOD3
TDI / GPIOD0
GPIOA0 / PWM0
GPIOA1 / PWM1
GPIOD4 / EXTAL
GPIOD5 / XTAL / CLKIN
GPIOB6 / RXD0 / SDA / CLKIN GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL GPIOB5 / TA1 / FAULT3 / CLKIN GPIOA9 / FAULT2 / TA3 / CMPBI1 GPIOA11 / CMPBI2 GPIOC4 / ANB0 & CMPBI3 GPIOC5 / ANB1 GPIOC6 / ANB2 / VREFHB GPIOC7 / ANB3 / VREFLB VDDA
ORIENTATION MARK
VCAP
VDD
VSS
GPIOA3 / PWM3
PIN 34 PIN 1
GPIOA2 / PWM2 GPIOA4 / PWM4 / TA2 / FAULT1 GPIOB0 / SCLK0 / SCL VDD VSS GPIOA5 / PWM5 / TA3 / FAULTA2 GPIOA8 / FAULTA1 / TA2 / CMPAI1
PIN 12
PIN 23
GPIOA10 / CMPAI2 GPIOA6 / FAULT0 / TA0 GPIOB2 / MISO0 / TA2 / PSRC0
GPIOC0 / ANA0 & CMPAI3
Figure 11-1 Top View, 56F8035/56F8025 44-Pin LQFP Package
56F8035/56F8025 Data Sheet, Rev. 6 150 Freescale Semiconductor
GPIOB3 / MOSI0 / TA3 / PSRC1
GPIOC1 / ANA1
GPIOC2 / ANA2 / VREFHA
GPIOC3 / ANA3 / VREFLA
GPIOB10 / CMPAO
RESET / GPIOA7
TCK / GPIOD2
VSSA
VSS
VCAP
56F8035/56F8025 Package and Pin-Out Information
Table 11-1 56F8035/56F8025 44-Pin LQFP Package Identification by Pin Number1
Pin # 1 2 Signal Name GPIOB6 RXD0 / SDA / CLKIN GPIOB1 SS0 / SDA GPIOB7 TXD0 / SCL GPIOB5 TA1 / FAULT3 / CLKIN GPIOA9 FAULT2 / TA3 / CMPBI1 GPIOA11 CMPBI2 GPIOC4 ANB0 &CMPBI3 GPIOC5 ANB1 GPIOC6 ANB2 / VREFHB GPIOC7 ANB3 / VREFLB VDDA Pin # 12 13 Signal Name VSSA GPIOC3 ANA3 / VREFLA GPIOC2 ANA2 / VREFHA GPIOC1 ANA1 GPIOC0 ANA0 & CMPAI3 VSS VCAP TCI GPIOD2 GPIOB10 CMPAO RESET GPIOA7 GPIOB3 MOSI0 / TA3 / PSRC1 Pin # 23 24 Signal Name GPIOB2 MISO0 / TA2 / PSRC0 GPIOA6 FAULT0 / TA0 GPIOA10 CMPAI2 GPIOA8 FAULT1 / TA2 / CMPAI1 GPIOA5 PWM5 / TA3 / FAULT2 VSS VDD GPIOB0 SCLK0 / SCL GPIOA4 PWM4 / TA2 / FAULT1 GPIOA2 PWM2 GPIOA3 PWM3 Pin # 34 35 Signal Name VCAP VDD VSS GPIOD5 XTAL / CLKIN GPIOD4 EXTAL GPIOA1 PWM1 GPIOA0 PWM0 TDI GPIOD0 GPIOB11 CMPBO TMS GPIOD3 TDO GPIOD1
3
14
25
36
4
15
26
37
5
16
27
38
6 7 8 9
17 18 19 20
28 29 30 31
39 40 41 42
10
21
32
43
11
22
33
44
1. Alternate signals are in italic
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 151
Figure 11-2 56F8035/56F8025 44-Pin LQFP Mechanical Information (1 of 3) Please see www.freescale.com for the most current case outline.
56F8035/56F8025 Data Sheet, Rev. 6 152 Freescale Semiconductor
56F8035/56F8025 Package and Pin-Out Information
Figure 11-3 56F8035/56F8025 44-Pin LQFP Mechanical Information (2 of 3) Please see www.freescale.com for the most current case outline.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 153
Figure 11-4 56F8035/56F8025 44-Pin LQFP Mechanical Information (3 of 3) Please see www.freescale.com for the most current case outline.
56F8035/56F8025 Data Sheet, Rev. 6 154 Freescale Semiconductor
Thermal Design Considerations
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) where: TA = Ambient temperature for the package (oC) RJ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = RJC = RCA = Package junction-to-ambient thermal resistance (C/W) Package junction-to-case thermal resistance (C/W) Package case-to-ambient thermal resistance (C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT JT PD = Thermocouple temperature on top of package (oC) = Thermal characterization parameter (oC/W) = Power dissipation in package (W)
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 155
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8035/56F8025:
* * Provide a low-impedance path from the board power supply to each VDD pin on the 56F8035/56F8025 and from the board ground to each VSS (GND) pin The minimum bypass requirement is to place 0.01-0.1F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are as short as possible Bypass the VDD and VSS with approximately 100F, plus the number of 0.1F ceramic capacitors PCB trace lengths should be minimal for high-frequency signals
* * *
56F8035/56F8025 Data Sheet, Rev. 6 156 Freescale Semiconductor
Electrical Design Considerations
*
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces. It is highly desirable to physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. Because the Flash memory is programmed through the JTAG/EOnCE port, QSPI, QSCI, or I2C, the designer should provide an interface to this port if in-circuit Flash programming is desired If desired, connect an external RC circuit to the RESET pin. The Resistor value should be in the range of 4.7k--10k; the Capacitor value should be in the range of 0.22f - 4.7f. Add a 3.3k external pull-up on the TMS pin of the JTAG port to keep EOnce in a restate during normal operation if JTAG converter is not present During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pull-up enable. The typical value of internal pull-up is around 110K. These internal pull-ups can be disabled by software. To eliminate PCB trace impedance effect, each ADC input should have a 33pf-10 ohm RC filter Device GPIOs have only a down (substrate) diode on the GPIO circuit. Devices do not have a positive clamp diode because GPIOs use a floating gate structure to tolerate 5V input. The absolute maximum clamp current is -20mA at Vin less than 0V. The continuous clamp current is -2mA at Vin less than 0V. If positive voltage spikes are a concern, a positive clamp is recommended.
* *
*
* * * *
* *
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. Table 13-1 56F8035/56F8025 Ordering Information
Device Supply Voltage
3.0-3.6 V 3.0-3.6 V 3.0-3.6 V
Package Type
Pin Count
44 44 44
Frequency (MHz)
32 32 32
Ambient Temperature Range
-40 to + 105 C -40 to + 105 C -40 to + 125 C
Order Number
MC56F8035 MC56F8025 MC56F8025
Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP)
MC56F8035VLD* MC56F8025VLD* MC56F8025MLD*
* This package is RoHS compliant.
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 157
Part 14 Appendix
Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table.
Table 14-1 Legacy and Revised Acronyms
Peripheral Reference Manual Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Data Sheet Processor Expert Acronym Memory Address Start End
Analog-to-Digital Converter (ADC) Module Control 1 Register Control 2 Register Zero Crossing Control Register Channel List 1 Register Channel List 2 Register Channel List 3 Register Channel List 4 Register Sample Disable Register Status Register Conversion Ready Register Limit Status Register Zero Crossing Status Register Result 0-7 Registers Result 8-15 Registers Low Limit 0-7 Registers High Limit 0-7 Registers Offset 0-7 Registers Power Control Register Calibration Register CTRL1 CTRL2 ZXCTRL CLIST1 CLIST2 CLIST3 CLIST4 SDIS STAT RDY LIMSTAT ZXSTAT RSLT0-7 RSLT8-15 LOLIM0-7 HILIM0-7 OFFST0-7 PWR CAL ADLLMT0-7 ADHLMT0-7 ADOFS0-7 ADPOWER ADLSTAT ADZCSTAT ADRSLT0-7 ADSDIS ADSTAT ADCR1 ADCR2 ADZCC ADLST1 ADLST2 ADC_CTRL1 ADC_CTRL2 ADC_ZXCTRL ADC_CLIST1 ADC_CLIST2 ADC_CLIST3 ADC_CLIST4 ADC_SDIS ADC_STAT ADC_CNRDY ADC_LIMSTAT ADC_ZXSTAT ADC_RSLT0-7 ADC_RSLT8-15 ADC_LOLIM0-7 ADC_HILIM0-7 ADC_OFFST0-7 ADC_PWR ADC_CAL ADC_ADCR1 ADC_ADCR2 ADC_ADZCC ADC_ADLST1 ADC_ADLST2 ADC_ADCLST3 ADC_ADCLST4 ADC_ADSDIS ADC_ADST T A ADC_ADCNRDY ADC_ADLST T A ADC_ADZCST T A ADC_ADRSL T0-7 ADC_ADRSLT8-15 ADC_ADLLMT0-7 ADC_ADHLMT0-7 ADC_ADOFS0-7 ADC_ADPOWER ADC_ADCAL ADC_ADCR1 ADC_ADCR2 ADC_ADZCC ADC_ADLST1 ADC_ADLST2 ADC_ADCLST3 ADC_ADCLST4 ADC_ADSDIS ADC_ADST T A ADC_ADCNRDY ADC_ADLST T A ADC_ADZCST T A ADC_ADRSL T0-7 ADC_ADRSLT8-15 ADC_ADLLMT0-7 ADC_ADHLMT0-7 ADC_ADOFS0-7 ADC_ADPOWER ADC_ADCAL 0xF080 0xF081 0xF082 0xF083 0xF084 0xF085 0xF086 0xF087 0xF088 0xF089 0xF08A 0xF08B 0xF08C 0xF094 0XF093 0XF09B
0XF09C 0XF0A3 0XF0A4 0XF0AB 0XF0AC 0XF0B3 0XF0B4 0XF0B5
Computer Operating Properly (COP) Module Control Register Timeout Register Counter Register CTRL TOUT CNTR COPCTL COPTO COPCTR COP_CTRL COP_TOUT COP_CNTR COPCTL COPTO COPCTR COPCTL COPTO COPCTR 0XF120 0XF121 0XF122
56F8035/56F8025 Data Sheet, Rev. 6 158 Freescale Semiconductor
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference Manual Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Data Sheet Processor Expert Acronym Memory Address Start End
Inter-Integrated Circuit Interface (I2C) Module Control Register Target Address Register Slave Address Register Data Buffer & Command Register Standard Speed Clock SCL High Count Register Standard Speed Clock SCL Low Count Register Fast Speed Clock SCL High Count Register Fast Speed Clock SCL Low Count Register Interrupt Status Register Interrupt Mask Register Raw Interrupt Status Register Receive FIFO Threshold Level Register Transmit FIFO Threshold Level Register Clear Combined & Individual Interrupts Register Clear Receive Under Interrupt Register Clear Receive Over Interrupt Register Clear Transmit Over Register Clear Read Required Interrupt Register Clear Transmit Abort Interrupt Register CTRL TAR SAR DATA SSHCNT IBCR I2C_CTRL I2C_TAR I2C_SAR I2C_DATA I2C_SS_SCL_HCNT I2C_IBCR I2CTAR I2CSAR I2C_DATACMD I2C_SS_SCLHCNT I2C_IBCR I2C_TAR I2C_SAR I2C_DATACMD I2C_SS_SCLHCNT 0xF280 0xF282 0xF242 0xF288 0xF28A
SSLCNT
I2C_SS_SCL_LCNT
I2C_SS_SCLLCNT
I2C_SS_SCLLCNT
0xF28C
FSHCNT
I2C_FS_SCL_HCNT
I2C_FS_SCLHCNT
I2C_FS_SCLHCNT
0xF28E
FSLCNT
I2C_FS_SCL_LCNT
I2C_FS_SCLLCNT
I2C_FS_SCLLCNT
0xF290
ISTAT IENBL RISTAT RXFT
I2C_INTR_STAT I2C_INTR_MASK I2C_RAW_INTR_ STAT I2C_RXTL
I2C_INTRSTAT I2C_INTRMASK I2C_RAW_INTRSTAT
I2C_INTRSTAT I2C_INTRMASK I2C_RAW_INTRSTAT I2C_RXTL
0xF296 0xF298 0xF29A 0xF29C
TXFT
I2C_TXTL
I2C_TXTL
0xF29E
CLRINT
I2C_CLRINTR
I2C_CLRINTR
0xF2A0
CLRRXUND CLRRXOVR CLRTXOVR CLRRDREQ CLRTXABRT
I2C_CLR_RXUNDER I2C_CLROVER I2C_CLR_TXOVER I2C_CLR_RDREQ I2C_CLR_TXABRT
I2C_CLR_RXUNDER I2C_CLROVER I2C_CLR_TXOVER I2C_CLR_RDREQ I2C_CLR_TXABRT
0xF2A2 0xF2A4 0xF2A6 0xF2A8 0xF2AA
56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor 159
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference Manual Register Name New Acronym Clear Receive Done Interrupt Register Clear Activity Interrupt Register Clear Stop Detect Interrupt Register Clear Start Detect Interrupt Register Clear General Call Interrupt Register Enable Register Status Register Transmit FIFO Level Register Receive FIFO Level Register Transmit Abort Source Register Component Parameter 1 Register Component Parameter 2 Register Component Version 1 Register Component Version 2 Register Component Type 1 Register Component Type 2 Register CLRRXDONE CLRACT CLRSTPDET CLRSTDET CLRGC ENBL STAT TXFLR RXFLR TXABRTSRC COMPARM1 COMPARM2 COMVER1 COMVER2 COMTYP1 COMTYP2 Legacy Acronym New Acronym I2C_CLR_RXDONE I2C_CLRACTIVITY I2C_CLR_STOPDET I2C_CLR_STAR_DET I2C_CLR_GENCALL I2C_ENABLE I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TX_ABRTSRC I2C_COMPARM1 I2C_COMPARM2 I2C_COMVER1 I2C_COMVER2 I2C_COMTYP1 I2C_COMTYP2 On-Clock Chip Synthesis (OCCS) Module Control Register Divide-By Register Status Register Oscillator Control Register Clock Check Register Protection Register Clock Divider Register Configuration Register Security High Half Register Security Low Half Register CTRL DIVBY STAT OCTRL CLKCHK PROT CLKDIV CNFG SECHI SECLO FMCLKD FMCR FMSECH FMSECL PLLCR PLLDB PLLSR OSCTL OCCS_CTRL OCCS_DIVBY OCCS_STAT OCCS_OCTRL OCCS_CLCHK OCCS_PROT FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO PLLCR PLLDB PLLSR OSCTL PLLCLCHK PLLPROT FMCLKD FMCR FMSECH FMSECL PLLCR PLLDB PLLSR OSCTL OCCS_CLCHK OCCS_PROT FMCLKD FMCR FMSECH FMSECL 0xF130 0xF131 0xF132 0xF135 0xF136 0xF137 0xF400 0xF401 0xF403 0xF404 Legacy Acronym Data Sheet Processor Expert Acronym Memory Address Start I2C_CLR_RXDONE I2C_CLRACTIVITY I2C_CLR_STOPDET I2C_CLR_STAR_DET I2C_CLR_GENCALL I2C_ENABLE I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TX_ABRTSRC I2C_COMPARM1 I2C_COMPARM2 I2C_COMVER1 I2C_COMVER2 I2C_COMTYP1 I2C_COMTYP2 End
0xF2AC 0xF2AE 0xF2B0 0xF2B2 0xF2B4 0xF2B6 0xF2B8 0xF2BA 0xF2BC 0xF2C0 0xF2FA 0xF2FB 0xF2FC 0xF2FD 0xF2FE 0xF2FF
56F8035/56F8025 Data Sheet, Rev. 6 160 Freescale Semiconductor
How to Reach Us:
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc. 2010. All rights reserved. MC56F8025 Rev. 6 02/2010

▲Up To Search▲

Price & Availability of 56F8035

	To Download 56F8035 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .